 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| XR88C681 FEATURES !" # $ $ % %& ' % '( $ %( )$*++$ '(% $ *++$ %(% ,- *(% ( ./ *( # ' % # *( 0 % ( 1 *( % # $ $ *( '( + 2' %( $ '( 2! '3 ((& !( *( 4 5 '3 .%" /5 '3 63.% 7" 28" 9' 9,* : $ 9,* : $% (+ '( / *( .( # ( 2(- %3 # $(( % # ;' '3 $- < ,( #, $ << ,( ,9 ,'3-% & GENERAL DESCRIPTION 25 (% %& ' % '( $ %( (% $ ' ('( % $(' ($% +& ( $ $ + $! %& ' % ' ('( ' % ( %( - '3- (% $%(- $ + % ( (''%% %$ %&%% $ & %$ ( $ ( $( ( 5==/= $(' ++% %( - # %( + ==.=6" ==/.==" ?=" ?=" /=!! $ /6!! (''%% +((% ORDERING INFORMATION Part No. 5==/=@ 5==/=7.< 5==/=,.= 5==/=,.< 5==/=@ 5==/=7.< 5==/=,.= 5==/=,.< ,- # (%& ( = 0 ,% % < ,( #, $ << ,( ,9 ,'3-% & > 0 ,% # % ( - + % '% # % < ,( #, $ << ,( ,9 ,'3-% & ( $ ( ( =6 7( *( $ ( %'( + &% $& $ $' ( - , ( ( /= $ (- ('% / $('% $ '$ 9 , ' -& APPLICATIONS ($( &%% ( ,., ( 2 + $ ('( &%% (% +('$ %( - $ '$ & " ( (- + ' $ %(& 2,#. =* '%% ($ (- + ' $ ' %( " $ (% '3-$ ( < ( ,#," = ( ,#," $ << ( ,9 Pin Package << ,9 < #, = ,#, < ,#, << ,9 < #, = ,#, < ,#, Operating Temperature Range > > > > < A=6 < A=6 < A=6 < A=6 XR88C681 5 5 5* 5* #, #,/ , ,> #, - + '% #, # , , , '( ' 9-(' , 8 8 8 8 $ -(%% % -(% $ -(%% % -(% * , # *% ( # #; (( * *( 0 .( %'( *% *++ * # # # $ '$ $$%% '$ > 1 B 22 #2# #2 # : #7 5.9: 5 Figure 1. Block Diagram of the XR88C681 XR88C681 PIN CONFIGURATION < #,/.# : < #,6.#2 << ;'' <1 #,<.#2# 1 #, B 5* 7 5* , ,1 ,6 ,> > = 1 < 6 / > 1 6 = 1 1= 22 1> 5 1/ 5.9: 16 5 XR-68C681CJ PLCC 1< 11 1 1 7 5 , , 1 ,< ,/ < / > = #,1 #, 1 #, B 5* 5* , ,1 ,6 ,> 1 6 > 07 7 1 #,1 6 #, < #, 1 < 6 / > = 1 < 6 / > = < 1 1= 1> 1/ 16 1< 11 1 1 1 = > / 6 < 1 ; #,<.#2# #,6.#2 #,/.# : #, 22 5 5.9: 5 5 , , ,< ,/ < / #7 / < > 7 1 #7 < 07 / 6 44 Lead PLCC 40 Lead PDIP, CDIP (0.600") 7 1 B 5* 5* , 1 6 > 07 1 < 6 / > = 1 < = > / 6 < 1 = > / 6 ; #, 22 5 5.9: 5 5 , < / #7 28 Lead PDIP (0.600") 1 XR88C681 PIN DESCRIPTION 44 PLCC/ LCC 40 DIP, CDP 28 DIP, CDIP Symbol 7 # Type Description No Connection. LSB of Address Input. (% ( " - ( $$%% # %" 1 %$ %' '( -(%% (( $('" $( - 2 $ B#2 ( % ( , Input Port 3. 0 ,% # B (% ( - ( #$" (% ( ' % %$ % ! ''3 ( + %( 5 B (% ( - ( ?$" (% ( ' %$ % ! ''3 ( + '( 5 < 6 1 < #, * 1 < 1 # # Address Input. Input Port 1. 0 ,% # (% ( ' % %$ % '( 9" C * $D ( * Address Input. MSB of Address Input. (% ( " - ( $$%% # %" %$ %' '( -(%% (( $('" $( - 2 $ B#2 ( % ( , Input 0. 0 ,% # (% ( ' % %$ % '(" C $D ( Write Strobe (Active-Low). CD (% ( ( (% % CD (% ' % + *% ( $ $%%$ -(%" (( %+ ''% (%( - $- + B Read Strobe (Active Low). CD (% ( ( (% % CD '% ' % + $$%%$ -(% " $ % Receive Serial Data Input (Channel B). % %(- (+(' ( + '' (% '($ +(% #+ ! '( ''3" 5*" (% %'(+($" $ (% %$ (%( - $- + (% ''3 No Connect. Transmitter Serial Data Output (Channel B). % %(- (+(' ( + '' (% %($ +(% (% (% $ ( (- 3( - % %( (% ($" $(%$" ' (% ( - ( ' 9, * : $ #+ ! %( ''3 (% %'(+($" 5*" %($ $ (% %(+$ + % ( (+ -(% +( - $- + (% ''3 1 #,1 5 # 5 ? # / > 6 / # # = > = 6 #, B # # / # > 5* # 1 = 7 5* < XR88C681 44 PLCC/ LCC < 40 DIP, CDP 28 DIP, CDIP Symbol , * ,1 5*.5 5*.5 ..G ,6 5G. 99.* ,> 5G.* Type Description Output 1 (General Purpose Output). (% ' % -$ + '( % '(" C * E% $D * Output 3 (General Purpose Output). (% ' % -$ + '( %4 C * % ( 5 ''3D 5*.5" C * '( 5 ''3D 5*.5" $( " '( C .( $&D ..G Output 5 (General Purpose Output Pin). (% ( ' % -$ + '( % $( " '(" * C'( $&D C'( # D ( $(' 5G.*. 99.* Output 7. (General Purpose Output Pin). (% ( ' % -$ + '( % $( " '(" C %( $&D ( $(' + * 5G.* Bi-Directional Data Bus. Bi-Directional Data Bus. Bi-Directional Data Bus. MSB of the Eight Bit Bi-Directional Data Bus. %+% , $ 3 ' (% % ' %(%( - + ( % > % (% (%$ ( (% C(-D" !' $( - # : '&' ( ? $ Signal Ground. No Connect. Interrupt Request Output (Active Low, Open Drain). #7 (% %%$ '' ' + + '(H% %3 ( ( - ' $(( % (% %(- ( ( %%$ - # (' ( $ ( -$ ' ' $(( % '%( - # E% % (( $ Bi-Directional Data Bus. Bi-Directional Data Bus. Bi-Directional Data Bus. LSB of the Eight Bit Bi-Directional Data Bus. %+% , $ 3 ' (% % % (% (%$ ( (% C(-D" !' $( - # : '&' ( ?$ Output 6 (General Purpose Output). (% ( ' % -$ + '( % $( " '( " C %( $&D ( $(' + 5G. 6 1 / < > 6 = / > = 1 1 6 > #. #. #. #. 1 < < 6 07 7 #7 ,B 6 / > = 1 < 6 / > = / < #. #. #. #. / 5G. ,/ 6 XR88C681 44 PLCC/ LCC 1 40 DIP, CDP > 28 DIP, CDIP Symbol ,< 5G. 99. , 5 ./ 5 5 5 .5 , 5 Type Description Output 4 (General Purpose Output). (% ( ' % -$ + '( % $( " '(" C'( $&D C # D ( $(' + 5G. . 99. Output 2 (General Purpose Output). (% ( ' % -$ + '( % & + + ( -4 %( /5 5 ''3 5 ./5 5 .5" '( 5 ''3 5 .5 Output 0 (General Purpose Output). (% ( ' % -$ + '( % '(" E% $ + Transmitter Serial Data Output (Channel A). % %(- (+(' ( + '' (% %($ +(% (% (% $ ( 3( - (- % %( (% ($" $(%$" ( - ( 9' 9,* : $ #+ ! %( ''3 (% %'(+($" 5 " $ (% %(+$ + %( (+ -(% +( - $- + ''3 No Connect. # Receive Serial Data Input (Channel A). % %(- (+(' ( + '' (% '($ +(% #+ ! '( ''3" 5 " (% %'(+($" $ (% %$ (%( - $- + ''3 Crystal Output of External Clock Input. (% ( (% ' '( + %($ + '&% $ ''( - $ ( %'( (% %$ #+ %'( (% %$" ! ''3 %(- % %($ (% ( # $ + 5==/= $(' + '( &" % % %& %(- ( +E '(% 8I $ <8I (% E( ' & ( '&% %'( & ! 9'( ''3 %(- Crystal Input. '( + %($ + '&% %( + 5.9: #+ %'( (% %$" ''( % % ' '$ + (% ( - $ (% ( % + (+ ! ''3 (% %($ 5.9: 1 = 1 11 1 1< 16 1 7 5 1/ 1 1 5.9: # 1> 11 < 5 / XR88C681 44 PLCC/ LCC 1= 40 DIP, CDP 1< 28 DIP, CDIP 6 Symbol 22 Type # Description Master Reset (Active High). %%( - (% ( '% ( -(%%" " #" #" ," ," $ ( (((I% #; / %%( - (% ( % %% . (" % , ,> ( (- %" $ '% %( ' % ( ( '( % ( 5 $ 5* % 3( - (- Chip Select (Active Low). $ % (% (%$ (% C(-D %+% , $ ( > $ (% CD Input 2. (General Purpose Input). (% ( ( ' % -$ + '( % C .( ! ''3D ( ..25 Input 6 (I-Mode). 0 ,% # ( (% ( ( ' % -$ + '( % 2! '( '3 + * 5* Interrupt Acknowledge Input (Z-Mode). '( 9 (% ( (% , H% % % # E% (%%$ & $(' B , %%% (% ( " ( ( $('% H% ( E% (% %('$" $ & ! '&' ( # '3 $- &' ( % $ , H% # '3 $- & '( - ' % + # ;' -(% #; $ % > Input 5 (I-Mode). 0 ,% # ( (% ( ' % ' +(-$ + '( % ! ''3 ( + %( + * 5* Interrupt Enable Output (Z-Mode). '( 8(- (% ( (% & C(-D 8" ( + +( - ' $(( % ' '% (% ( -$ --$ CD #+ #2# # 2 # ( (% CD #+ #2 (% CD '% + #2# ( " #2 ( -- C(-D ' #2# % --$ C(-D % (%%$ # E% , #7 ( (% --$ CD #+ #2 (% CD '% % E%$ # " #2 ( ( CD" - # (' ( " ( , % ( 3$ CD ' $ <1 1 #,< 5 #2# ?$ # Input 4 (I-Mode). 0 ,% # ( (% ( ( ' % ' +(-$ + '( % ! ''3 ( + '( + 5 Interrupt Enable Input (Z-Mode). '( 8(- #+ (% '((- ( (% -(' C(-D" (% ' + - ( - %3$ # E%% , #+ (% ( (% -(' CD" (% ( (($ + - ( - & # E%% , Most Positive Power Supply. 1 16 / # < 1/ > #, ..25 #,/ 5* # : # < 1> # < 1> # < 1= #,6 5* #2 ?$ # < 1= <1 1 # << < = ; ,B > XR88C681 DC ELECTRICAL CHARACTERISTICS1, 2, 3 Test Conditions: J >" ; J 6; 6K %% (% %'(+($ Symbol ;#9 ;#8 ;#8 ;#85 ;9 ;8 ##9 ##929 #59 #59 #5#8 #58 #99 # # # Parameter # 9 ;- # 8(- ;- # 8(- ;- ((& # 8(- ;- 5.9: 9 ;- 8(- ;- # 93- ' ,( 93- 5 # 9 5 # 9 5 # 8(- 5 # 8(- *% ( 93- ( 93- , & < , & < Min. 6 < < 6 1 Typ. Max. = ; ; < 6 A1 Unit ; ; ; ; ; ; * * * * * Conditions J 66 6 #9 J < #8 J <* ;#7 J ; ;#7 J ; ;#7 J ;#7 J ; ;#7 J ; ; J ; ; J ; '( $ $& $ > / 1 6 * * Notes 1. Parameters are valid over the specified temperature and operating supply ranges. Typical values are 25C, V CC = 5V and typical processing parameters. 2. All voltages are referenced to ground (GND). For testing, input signal levels are 0.4V and 2.4V with a transition time of 20ns maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V as appropriate. See Figure 50. 3. For prime grade N, P, J, L, M, ML, V CC = 5V + 10%. 4. Measured operating with a 3.6864MHz crystal and with all outputs open. = XR88C681 AC ELECTRICAL CHARACTERISTICS 1, 2, 3 Test Conditions: J >" ; J 6; 6K %% (% %'(+($ Symbol 2 8 8 B 8 B Parameter 22 ,% B($ 1 ( " B 9 1 8$ ( + " B 9 ( " B 9 8$ ( + " B 8(- " B ,% B($ ;($ + 9 *% ( - + 8(- ( B 8(- 8$ ( + B 8(- 8(- ( * $% $. B(%6" / #2 & ( + #2# # : ( 9> 6 < # : 8$ ( + 8(- #2# ( 9 #2 & ( + #7 9 , # ( . 9 , # 8$ ( + . 8(- , ;($ + B. 8(- #7 ,1 ,> %$ % # % 8(- +4 + # % % *(% ( # #, + # %3 ( # 5.9: 2! 8(- 9 ( 5.9: &% 2! E '& >1> 6 Min. 6 / >6 Typ. Max. Unit * % % % % % % % % % % Conditions Reset Timing (See Figure 51) XR88C681 Read and Write Cycle Timing (Figure 52)4 Z-Mode Interrupt Cycle Timing (Figure 53) # # # 8 2# 2 , ,8 , % % % % % % % % Port Timing (Figure 54)4 Interrupt Output Timing (Figure 55) # 1 1 % % Clock Timing (Figure 56) 9: 9: % 8I XR88C681 AC ELECTRICAL CHARACTERISTICS 1, 2, 3 (CONT'D) Test Conditions: J >" ; J 6; 6K %% (% %'(+($ Symbol 5 +5 Parameter .( 2! '3 8(- 9 ( #, .( 2! '3 E '& 5 $ 5 2! 8(- 9 (= 5 $ 5 2! E '& /5 5 5 & 5 2! 9 5 & 5 # 9 5 ( 5 2! 8(- 5 8$ ( + 5 2! 8(- Min. >1> Typ. Max. Unit % 8I % Conditions Clock Timing (Figure 56) (Cont'd.) / 16 6 8I 8I % % % % Transmitter Timing (Figure 57) 5 5 58 < Notes 1. Parameters are valid over the specified temperature and operating supply ranges. Typical values are 25C, V CC = 5V and typical processing parameters. 2. All voltages are referenced to ground (GND). For testing, input signal levels are 0.4V and 2.4V with a transition time of 20ns maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V as appropriate. See Figure 50. 3. AC test conditions for outputs: CL = 50pF, RL = 2.7k* to V . CC 4. If CS is used as the strobing input, this parameter defines the minimum high time between CSs. 5. Consecutive write operations to the same register require at least three edges of the X1 clock between writes. 6. This specification imposes a 6 MHz maximum 68000 clock frequency if a read or write cycle follows immediately after the previous read or write cycle. A higher 68000 clock can be used if this is not the case. 7. This specification imposes a lower bound on CS and IACK low, guaranteeing that they will be low for at least one CLK period. 8. The minimum high time must be at least 1.5 times the X1/CLK period and the minimum low time must be at least equal to the X1/CLK period if either channel's Receiver is operating in external 1X clock mode. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS1 & ;- >; - /6 6 ;-% ( %' 0 $ 6; A>; 1. Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the "Electrical Characteristics" section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. XR88C681 2. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive stat- ic charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltage larger than the rated maximum. XR88C681 SYSTEM DESCRIPTION 5==/= ' %(%% + ( $ $ " +$! ' ('( ' %L ' ' %(%( - + ( %( $ '( 2' ' + & ( $ $ & -$ + ( - $ $ $ + ' ( +' ($ - + '%%% ( ( ( + ' % ( - %$ + ' '( $ %( & %'$ + + 1 ( & - $ +(!$ ( %" + ''3 $($ + ( ' .(" + ! & %($ ! /! ''3 ( - %' + 1 $(++ +(!$ ( % ' $('& + '&% ' '$ '%% ( % + ! ''3 ((& ( $ $ & - ( - %$ + '( $ %( + ' ' 3% '( + %( %$ ' ('( % %' % '%$ ( %&%% '( $ (% E$$ ++$ $ %( $ (% $++$ ( '( # % ( $ ( ((I (%3 + '( $ $' $ ( ( $( ('( % % ($% + ' '((& ( (( %(%%( + $(' ++ + '(( - (% +" % ( - %% + $ % ($% - % / ( ' .( (' & % %$ % - ( - %" > ( (% ( $ = ( (% + < ( #, $ << ( ,9 '3-% & PRINCIPLES OF OPERATION Figure 1 % % '3 $(- + % (%$ ( '3 $(-" ' %(%% + +( - M + '( '3%4 *% *++ # # , ( ('( % $ * ( (( - , A. DATA BUS BUFFER $ % ++ ($% ( +' ( (( '( $ ! $ %% # (% ' $ & ( ' '3 $ %+% 3 ' % , $ B. OPERATION CONTROL BLOCK ' -(' + ( '3 '(% ( - ' $% + , $ - % %(- % (% %'( % + ( *'3 + '( % % % ( +' % + $(' '(+('&" ( (% % %( + -(% $$%% '$( -" $ $ '$( - + ' $% % $ %" (&" ' ('( ' %" % % .( $( - C%% -(%D ( $ ' ('( + ' % - - ( *'3 ( *'3 ( ' + ' %$ +( - ( %(- % $$%% # %" 1 B 22 B %( - /= +(& '%%" ( E( % - -(' # +'( - /= (& ,'%% ' %(& '($ & ( '$( - % + ! -(' $('%" % $('$ ( Figure 2 XR88C681 .B B 2 ''3 22 22 Figure 2. External Logic Circuitry required to interface a 6800 Family Processor to the XR88C681 Device B.1 DUART Register Addressing $$%%( - + ( -(%% + (% % $ ( Table 1 Please note that some of the registers are "Read Only" and others are "Write Only". 2' ' (% ($$ ( +( - $$('$ $$%% -(%% $ -(%% $ -(%% $ % -(%% '3 ' -(%% '( 8$( - -(% 8 $ %( 8$( - -(% 8 $$(( &" ' ( % +( - -(%% %.' ' % # % -(% # %3 -(% %3$ # % -(% # ;' -(% !((& -(% $ +( &" % ' ( % -(%% % + '( % %( $ ' ('( " %' % % $ ' %.(% , , -(% #, # , +(-( -(% .( *& -(% 9 .( 9 *& -(% 1 XR88C681 Address (Hex) 1 < 6 / > = * Read Mode Registers Register Name $ -(%" % -(%" %3$ # % -(% ! 8$( - -(%" # , - -(% # % -(% .( *& -(% .( 9 *& -(% $ -(%" * % -(%" * 22;2 ! 8$( - -(%" * # ;' -(% # , 8* #; #, Symbol " # 8 #, # 9 *" * * Write Mode Registers Register Name $ -(%" '3 ' -(%" $ -(% ! 8$( - -(%" !((& -(% # %3 -(% .( *& -(% .( 9 *& -(% $ -(%" * '3 ' -(%" * $ -(%" * ! 8$( - -(%" * # ;' -(% , +(-( -(% , ,> , *(% $ , *(% $ Symbol " 8 # 9 *" * * * 8* #; , 2 .( $ .( $ ,* ,* Table 1. DUART Port and Register Addressing Note: The shaded blocks are not Read/Write registers but are rather "Address-Triggered" Commands. Table 1 ( $('% ' ' (% E($ ( $ -(%% %%'($ ( ' + % $ -(% (% (% C$ -(%D ( ( '(.%&% 22 ' ( (% C( ( - D ' -(% Please note that the suffix "n" is used at the end of many of the DUART registers symbols in order to refer, generically, to either channels A or B 8" ' % + ( ( %(+ + $$%% + -(% + -(%" ($(& +( - & $ B( ''%% -(% ( ( ' ( C( D -(% ( $ % ''% ( C22 ,#72D ' $ % ( 3$ C22 ,#72D ' $ ' (%%$ & (( - ( $ ( ' H% $ -(% +" $ -(%%" (( -( < XR88C681 ' " % -(' $$%% +% $ + '( % + ' $ & $ -(%% $(%'%%$ ( $( ( Section G.3 B.2 Command Decoding 2' ' (% E($ ( $ -(% # - " + % $ -(%% .$(% %(" .$(% '(" - ( +'((( - %(% + (%' % ' $% ( + + ' $ -(% (% % $ ( Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Miscellaneous Commands ( - ! Enable/Disable Receiver J 7 - J 2 ! J (% ! J 7 ($ $ % Enable/Disable Transmitter J 7 - J 2 ! J (% ! J 7 ;($ % Table 2. (CRA, CRB) Bit Format for Command Registers of Channels A & B + '( + ( + $ -(%% (% +(& %(-+$ (% ( (% %$ ( $(% %( $. '( ( + $ -(% (% %$ ( 3 %(% + (%' % ' $% Table 3 $+( % ' $% %%'($ ( ( + $ -(%% Please note that the upper nibble commands 116 through B16 effects only the performance of Command Register's Channel 8" ' $% / $ / ++'% %&% '( ( Bit 7 Bit 6 Bit 5 Bit 4 Description Null Command. Reset MRn Pointer. %% H% ( ( Reset Receiver. % ( $(($ ' '( % (+ 8$ % % ($ '( (% $(%$ $ # (% +%$ Reset Transmitter. %% ( $(($ ' %( % (+ 8$ % $ ($ 5 (% +'$ (- Table 3. Miscellaneous Commands, Upper Nibble of all Command Registers, Unless Otherwise Specified (Cont'd Next Page) 6 XR88C681 Bit 7 Bit 6 Bit 5 Bit 4 Description Reset Error Status. % '($ *3 *" ,(& 2 ,2" ( - 2 2 $ 2 2 %% (%" N>41O '(+('&" (+ 2 $" + (' ' (% % C*'3D 2 $" (% ' $ ( % + '( 2 # $('% ( % -(% # *'3 2 $" ' ( ,2" 2" 2" * ''%" ( ' ( +--$ ( % -(%" ( (% ' $ (% (%%$ #+ 2 $" + (' ' (% % C' 2 $D" ' % + % -(% + ,2" 2" $ * +'$ '' & '' %(% # C' 2 $D" % + % ( $('% (% %$ & '' (% + 8 2 ( $(' (% &% % $ % C*'3 2 $D ( $('" $ E(% (% ' $ % Reset Break Change Interrupt. % ' H% 3 ' - ( %% ( Start Break. '% 5 %( % $ % 3 #+ %( (% &" % + 3 & $&$ ( (% #+ %( (% ' (" 3 -( % %(%%( + % ''% ( 8 (% '$" (I" 52, % + 3 ( -( Stop Break. 5 ( ( - (- (( ( (% 5 ( ( (- + ( ( + ! ''" (+ &" (% %($ Set Rx BRG Select Extend Bit. % ' H% C'( *0 ' 2! $ *(D Clear Rx BRG Select Extend Bit. % ' H% C'( *0 ' 2! $ *(D Set Tx BRG Select Extend Bit. % ' H% C %( *0 ' 2! $ *(D Clear Tx BRG Select Extend Bit. % ' H% C %( *0 ' 2! $ *(D Table 3. Miscellaneous Commands, Upper Nibble of all Command Registers, Unless Otherwise Specified (Cont'd) / XR88C681 Bit 7 Bit 6 Bit 5 Bit 4 Description Set Standby Mode (Channel A). B (% ' $ (% ( 3$ ( $ -(% " (% $ + ' + %(%" '(%" ' .( $ $$(( '('(% ' ( % $& $ Please note that this command effects the operation of the entire chip 7 ( (% %$ & $ % & ( 3( - C2 #;2 2D ' $ Reset IUS Latch (Channel B). B (% ' $ (% ( 3$ ( * $ -(%" $ (% ( - ( ?$" ( '%% # $(' # ' % (%" ( " ( '% #2 -- C(-D Set Active Mode (Channel A). B (% ' $ (% ( 3$ ( $ -(% " (% $ + $& $ $ %% ( Set Z-Mode (Channel B). B (% ' $ (% ( 3$ ( * $ -(%" (% ' $(( $ ( ?$ $($ $(%'%%( + H% ( ( ( ?$" ,% % Section C.6.2 7 ( + = ( #, '3-$ $('% Reserved. Reserved. Table 3. Miscellaneous Commands, Upper Nibble of all Command Registers, Unless Otherwise Specified (Cont'd) # $$(( ' $% (' ( - ' $ -(%%" % ++% C $$%%(--$D ' $% % ' $% (%$ ( Table 1" C , 7 20#2 2#70DL $ + ($ (+($ & ( C%$$D ( Table 1 '(+('&" % ' $% 4 72.#2 7 , 72.#2 7 2 , , *# 7 92 , , *# 7 & ( - ( " ( % % (% '$ (% .( ( ( (( ' ( - $($ $(%'%%( ( ( + .(" % % Section D.2 ! + $$%%(--$ ' $% (% C2 , , *#D $ (% ' $ (% ( 3$ & +( - ( + $ $$%% 2/ B % ( 3% (% ' $" .% (% %( - '( (% CD (( , , -(% (%" (( , %'(+($ %" ' -$ % + ( % ' % + ( $(($ (% (( , 8 '" (+ ,NO (% % CD" % + '% $( - ( " ," (% % -(' CD %E &" ' ( 3 + C2 , , *#D ' $ % C92 , , ,#7D ' $ $($ $(%'%%( ( ( + ,%" % % Section F 2' + % ' $% ( 3$ & ( $( - (( - $ ( '% $( - $$%%% % %'(+($ ( Table 1 2!4 72.#2 7 (% ( 3$ & '$ + $( - $$%% 2/ Please note that this "Read Operation" will not result in placing the contents of a DUART register on the data bus. > XR88C681 C. INTERRUPT CONTROL BLOCK # *'3 % % & ( C# ( D ( ( '$% ( E% %(- #7" (' & -$ %%$ '' ' + & + +( - %4 %( 8$ -(% * $& '( 8$ -(% * $& Register # # # #; '( # * 2 $ + '($ *3 ( % * 2 $ + .( '$ - + ( ( %" #," #," #," #,1 # *'3 ' %(%% + # % -(%% #" # %3 -(%% #" %3$ # % -(%% # $ # ;' -(% #; Table 4 (%% % -(%%" ( $$%% '( (( Address Location (in DUART Address Space) 6/ $ & 6/ B( & / $ & / Description # % -(% # %3 -(% %3$ # % -(% # ;' -(% Table 4. Listing and Brief Description of Interrupt System Registers $ % + ' + % -(%% $+( $ C.1 Interrupt Status Registers (ISR) ' % + # ( $('% %% + ( ( ' $(( % #+ & (% (( % -(%% --$ C(-D" '% $( - ' $(( % (% Bit 7 Input Port Change J 7 J G% Bit 6 Delta Break B J 7 J G% Bit 5 RXRDY/ FFULLB J 7 J G% Bit 4 TXRDYB J 7 J G% ''( - # - " ' % + # ( ( $(' '%%" %' % + # E% + +" & ( %(' ( + %$ -( & $( ( (% -(% # %3$ # % -(% (+ + # (% % $ ( Table 54 Bit 3 Counter Ready J 7 J G% Bit 2 Delta Break A J 7 J G% Bit 1 RXRDY/ FFULLA J 7 J G% Bit 0 TXRDYA J 7 J G% Table 5. ISR Bit Format $+( (( + ( - ( $ ' + % (% (% % $ ISR[7]: Input Port Change of State #+ (% ( (% -(' CD" ' - + % % $'$ # , ( % #, #,1 % $ %(' (% ( & $( - #, (+ #N>O J #N>O (% '$ , % $ # , +(-( -(% #, *& $( - #," % ( $( 4 = ( $(($ # , ( ' -$ % +( % + ($ ( %" +( - + $($ $%'(( + #," % Section F Please note that in order to enable this Interrupt Condition, the user must do two things: B( ( $ ( + !((& -(%" N14O # (% %" % (% %'(+&( - (' # ,( % %$ (-- C# , -D # E% XR88C681 B( -(' CD #N>O ISR[6] Delta Break Indicator - Channel B B (% ( (% %" ( ( $('% * '( % $'$ -( ( - $ + '($ 3 * (% ( (% '$ % , ( 3% ' * C22 *2 : 8 702 #72 ,D ' $ % Table 3 ( +( ( H% % % *2 : ' $(( " % % Section G.2 ISR[5] RXRDY/FFULL B - Channel B Receiver Ready or FIFO Full + '( + (% ( (% %'$ & -( *N/O #+ -$ % '( $& ( $(' 5G*" ( ( $('% % '' + $ (% ( 8* $ (% $& $ & , (% ( (% % '' (% %+$ + '( %(+ -(% 8* $ (% '$ , $% 8* #+ %( ''% ( 8* + $ ( " ( ( % -( + 8* (% C$D #+ (% ( (% -$ % # + ( $(' 99*" ( (% % '' (% %+$ + 8* $ %+ '%% 8* ' + (% ( (% '$ , $% 8*L $ & C( -D # " 3( - + ! '' #+ '' (% (( - ( '% 8* (% +" (% ( ( % -( + $ ( " '' (% $$ ( 8* Note: If this bit is configured to reflect the FFULLB indicator, this bit will not be set (nor will produce an interrupt request) if one or two characters are still remaining in RHRB, following data reception. Hence, it is possible that the last two characters in a string of data (being received) could be lost due to this phenomenon. '% $$ ( 8* ( %( (% $(%$ ( %($ ISR[3] Counter Ready # #2 $" . .( ( % #N1O ' ' '&' + % %E ( ,1 ( #N1O ( '$ & ( 3( - C, 72D ' $ * ( ( $" ( #2 $" C, 72D ' $ ( % . # 72 $" (% ( (% % ' '% ( ' / $ (% '$ ' (% %$ & C, 72D ' $ B .( (% ( 72 $" C, 72D ' $ ( % .( ISR[2]: Delta Break A - Channel A Change in Break %%( + (% ( ( $('% ' '( % $'$ -( ( - + $ + '($ 3 * (% ( (% '$ , ( 3% ' C22 *2 : 8 702 #72 ,D ' $ ( +( ( H% % % *2 : ' $(( " % % Section G.2 ISR[1] RXRDYA/FFULL A - Channel A Receiver Ready or FIFO Full + '( + (% ( (% %'$ & -( N/O #+ -$ % '( $& ( $(' 5G " (% ( ( $('% (% % '' + $ ( 8 " $ (% $& $ & , (% ( (% % '' (% %+$ + 8 $ (% '$ , $% C%D 8 #+ %( ''% ( 8 " +( - $ ( " ( ( % -( + 8 (% C$D #+ (% ( (% -$ % # 8 + ( $(' 99 " ( (% % '' (% %+$ + 8 $ & %+$ '' '%% 8 ' + (% ( (% '$ , $% 8 #+ '' (% (( - ( '% 8 (% +" (% ( ( % -( " +( $ ( " '' (% $$ ( 8 Note: If this bit is configured to reflect the FFULLA indicator, this bit will not be set (nor will produce an interrupt request) if ISR[4] TXRDYB - Channel B Transmitter Ready (% ( (% $(' + 5G *" *NO (% (" %" ( $('% 8* (% & $ (% $& '' '' + , ( (% '$ , (% '' 8*L $ (% % -( " '' (% %+$ 5G* (% % %( (% ( ((& $ $ (% '$ %( (% $(%$ XR88C681 one or two characters are still remaining in RHRA, following data reception. Hence, it is possible that the last two characters in a string of data (being received) could be lost due to this phenomenon. Therefore, the user is advised to read RHRA until empty. '% $$ ( 8 ( %( (% $(%$ ( %($ C.2 Interrupt Mask Register (IMR) # %3 -(% (% CB( &D -(% (' % % %' ' $(( % ( '% (%% # E% '%% # $%" % % ( + %3( - '3( - '( ' $(( % + '%( - (%% # E% +" (+ + # (% %% (& % % # 8" + ' %%" *( + # (% % $ Bit 3 Counter Ready J ++ J Bit 2 Delta Break A J ++ J Bit 1 RXRDY/ FFULLA J ++ J Bit 0 TXRDYA J ++ J ISR[0]: Channel A Transmitter Ready (% ( (% $(' + 5G " NO (% (" %" ( $('% 8 (% & $ (% $& '' '' + , ( (% '$ , (% '' 8 L $ (% % -( " '' (% %+$ 5G (% % %( (% ( ((& $ $ (% '$ %( (% $(%$ Bit 7 Input Port Change J ++ J Bit 6 Delta Break B J ++ J Bit 5 RXRDY/ FFULLB J ++ J Bit 4 TXRDYB J ++ J Table 6. IMR Bit Format #+ % (%% '( ( " .% %$ ( CD ( (( #" '% $( # $(( 9(3(%" $(% %3 '( ' $(( '%( - ( " % %$ ( CD ( '( '% $( - ' $(( ( % % $ ( / CD% (% -(%% Please note that IMR is a Write Only Registers, and can therefore not be read by the processor. C.3 Masked Interrupt Status Register (MISR) ' + # -(% (% %('& %% + 7( - # $ # - # J N# %O N# %O ((( + # (' ( % & $( - # (% (% (( # ' -- C(-D $ ( '% $( - ' $(( % & $ & # +" %" +( - $( - # % -(%" ( 3 (%( % +L $ !' C(&(D 7 + # $ # ' % ( ' # (% CB( &D -(% $ ' $ & '%%" ' % + # ( %$ ( %&% &" + ' $$(( $ $ %+ $ E($ % (% '((& ' (( $ ( % + # C.4 Interrupt Vector Register, IVR (% -(% (% & %$ + # ;' - ( (% ' $$ ( %'( ?$ B( ( (% $" ' % + #; (% &('& $ %( - $$%% + % # (' ( (%" ( #$" # ;' - ( (% &('& +$ ++'( B (% ( - ( #$" #; ' %$ % - % $.( -(%% + #;" ( (% ( - ( ?$ (% % $ ( Section C.6 C.5 Limitations of the DUART Interrupt Structure # ' ++$ & % % - - ( % ( % % '( 8 $ 8 # ' $(( %L .( $& ' $(( " $ ' -% ( *3 $(( '( 8" %($ + C *3 $(( D *" H% # ' $% + ( E%% $ XR88C681 '( % %' % ,(& 2 ,2" '( 2 2" ( - 2 2 % $% ++ % ((& ' +(- + % & '' ' + & + % ' $(( % +" %% % (% ( ( % % + C 9( 3 9&D ''3( - %' %' % " % (% $(%$ C($D '($ $ & +E & $( - % -(%L $ ''3( - + & I ( % (% (% %'(& '% (+ % % % 2 $ C'D N6O J C.6 Servicing DUART Interrupts # %('( - ( 5==/= +% ( $ '-(%4 #$ $ ?$ #$ % (%('& +$ % C# D $ 9(3(%" ?$ % +$ % C?(-D $ B (% ( - ( ?$" ( ' = ( C( 'D $ %" , " $( - C# '3 $-D # : '&' , ( $ (% ( ' + *%" $ $( + # ;' $ '( + ( ( %(' ( " ( %&% & $$(( &" ?$ -(% % $ ' (((I ( E%% - % ( $('% (% (% $(%'%%$ ( - $( ( Section C.6.2 B (% ( - ( #$" ( ($ & ( ' ( +( , " $( - # : '&' # ;' ( +( " & % - ' ( # (' ( " (% ''(%$ ! ( ( #$ +( - $ % % % ( 3 C ?$D ' $" ( $ ' $ ( ?$ - #$ % +$ % C# D $" $ ?$ % C?(-D $L (% $% % %$ & ( ?$ ( +'( - ?(- (''%%" ( #$ ( +'( - # (''%% $((%( #$ $ ?$ (% '%%& - C'D ( % #+ & ( +'( - +( - (''%%%. ('' %" % ( #$ =6* , ==* , ==6* , /=8* ?=* , # $% $ 8" %$ ( - ( ?$ ( +'( - +( - (''%%%. ('' % ===* , ==/* , ==/ =<=/* ,% , (* , ?=* , # $% ! + %'( % ( ($ $($ $(%'%%( % + .(''%% ( +'( - $ ( '%%( - ' + ( $ (''%%% (% $(%'%%( " $($ $%'(( + #$ # '%%( - $ ?$ # '%%( - ( - C.6.1 I-Mode Interrupt Servicing ( ( #$ +( - + #" $ % # - " , ( +'( - ( - ( #$" ( + '( % +%" $( - ( %('( - #+ E(% ( %(' + , " ( ( %%% #7 ( , ' , % $'$ ( E%" ( ( $( '( + ( ( %(' ( " $ ( ' - ' '( , ( ''(% + (% ( ($( - C# '3 $-D %(- & + ( '( ( ' , % (( $ '%% + H% ( E%" ( - (% #7 ( , ( !( C D ( %(' ( $ ( % '%%( - # - '% , % ' & % ' ( ( %(' ( " ( +'$ ( #$ (' # ,'%%( 2! ;'$# ,'%%( Direct Interrupt Processing #+ , &% C(' # ,'%%( -D ' , % $'$ ( E%" $ % '$ (% ' ( %'( " , ( ' - ' %'(+(' '( ( %&% & XR88C681 , % & $(' ( %" (% C'( D (% +(!$ & , '('(& (%+ 2!4 #+ #7 ( E% ( ( " + =6* " (% %%$" , ( ' - ' '( 1/ ( %&% & (% '( (% +(!$ & '('( $%(- + =6* , $ ' ' -$ & % (External) Vectored Interrupt Processing , % & (% + + ( '%%( &('& # '3 $- ( (% C# :D C#7 D ( %$ - C( 'D ( +( *%" ( ! $ C2! D (% %$ $%'( (% + + '$( '%%( -L * P/* C =6* == * , Type of Interrupt Processing (' 2! ;'$ '% '( + ( %(' ( (% $( $ & $ C! D % , %" %' % == $ ==6* ," (% C( 'D ( +( (% & '$ + 99 ( %'( %'( C2 %( D '( + (% C2 %( D (% +(!$ & , '('( $%(- #+ % &% (% ' + ( '%%( -" .% (% % %( + ( %( ( ( %(' ( " ' $(( ' ( %'( ( %(' ( %($% (% '( ( & 2' + % # ,'%%( - ' (E% ( % $ ( - $( ( +( - %'( % % ( $ (" %$ ( - ( #$" ( +'$ * ,.* % $ ( Table 7 Table 7 % % % & + ( '%%( - (% &$ & ' + % * ,%.* % Comments =6 * % ! # E% ( %4 #7 $ #7 == * , ( % + = $(++ '$% + C 99D ( %'( % # (' ( % == , $ ( ( ' 3 $- " #7 " (' ' %$ C-D C 99D ( %'( % *% ==6* , (' $ 2! ;'$ ==6 * , % C('D ! # E% ( %4 >6" /6" $ 66 $$(( &" (% * , % !' % C'D ( % % $% == * , /=8 * % %( - C%3D ! # E% ( L #) ?= , %% !' % ' % % $ + == , ?= ( ' 1=8 ( %&% & (+ #7 ( E% ( (% %%$ /=8* ?=* , # $ ?=* , (' 2! ;'$ (' # Table 7. Summary of * P/* C and their types of Interrupt Processing (I - Mode) ( +( % $ ( Table 7 (% $(%'%%$ ( $( ( +( - %'( % XR88C681 C.6.1.1 8051 Microcontroller =6 +(& + ('' % (% +'$ & # $ '% ( (& + ((% + % ((% ( '$4 '( %( = ( #. , ,1 / ( (% <3 &% + = &% + Figure 3 % % '3 $(- + =6 ('' " $ Figure 4 % % ( + (% $(' #7 #7 ( =1.=6 ( ( ( , 25 ( =1.=6 ( ( = &% =1.=6 = &% : =1.=1 <: =6 =: =6 # -(%% , %'( *% #. ,% ( , 2 92 ,27 , , , ,1 5 5 Figure 3. Block Diagram of the 8051 Microcontroller 1 XR88C681 , , , ,1 ,< ,6 ,/ ,> 1 < 6 / > = < 1 1= 1> 1/ 16 ; , , , ,1 1 ,< < ,6 6 ,/ / ,> > 2 92 ,27 ,> 6 ,/ < ,6 1 ,< ,1 , , , = 8051 Microcontroller 1< 11 1 1 1 = > / 6 < 1 ,1 5 ,1 5 ,1 #7 ,11 #7 1 ,1< < ,16 6 ,1/ B / ,1> > 5 9 = 5 9 ; Figure 4. Pin Out of the 8051 Microcontroller =6* ' %(%% + < =( #. % + % % + '( %" % ( $(%'%%$ Port 0 (P0.0 - P0.7) (% (% $% ( % 1 1 + =6 # # ( ( ' $%(- %" ( (% %$ % - % #. - $%(- % ( ! &" ( '% (!$ $$%% $ $ % > Port 2 (P2.0 - P2.7) , ,( % = (% $% ' + '( % - % #." % (- & + < Port 1 (P1.0 - P1.7) , (% $$('$ #. ( % = ( %" $%(- $ % ," ," ," " ( + ( +'( - % E($ 7 ( + '( % %%(- $ + , ( %L % & %$ %& + ( +'( - ! $('% 2!'( % =1.=6 #%" (' % , $ , ( % #. ( % % ! ( % ($ ( $$%% % + $%(- % ( ! '$ & + 6/ &% + ! $ & = 6 XR88C681 Port 3 , 1 (% $% ( % > # $$(( + '( ( - % - % #." % ( % ( + '( % 2' + % ( % %" % (%$ ( Table 8 Bit ,1 ,1 ,1 ,11 ,1< ,16 ,1/ ,1> Name 5 5 #7 #7 Alternate Function '( + ( , %( + ( , 2! # 2! # (. 2! # (. 2! # 2! & B( 2! & $ B Table 8. Alternate Functions of Port 3 Pins =6 % % % $$(( ( % (' ( +'( - 5==/= (% % ( % 4 Interrupt #7 #7 Location 18 18 ALE - Address Latch Enable #+ , (% %$ ( (% $ % $ % $ & + $$%% % 92 (% %(- '% $$%% ( ! -(% $( - +(% + + & '&' ' (% (% $ " , ( % ( + $ ( $( - %' $ + + & '&'" $ %+ 3% ' Table 9. Interrupt Service Routine locations (in Code Memory) for INT0 and INT1 +" (+ % (% %( - ( + % ( % % ( E% ( " % % ( % ( ( %(' ( ' $(( ' ( %'( ( %(' ( (% '$ + % $$%% '( % #+ =6* (% E($ ( +' ! ' % ( $ & %' + %(I% - 6/ &%" ,% $ , % %$ % $$%% $ $ ( % , ( + '( % (!$ $$%%.$ % ( - +(% + + & '&'" , ( % $$%% & ( - %' $ + + & '&' , ( % ($('( $ % , ( %$ % $$%% & 92 $ % + ><91>1 % ' $(' ' %$ $(! $$%% $ % %(- % Figure 5 % % %'(' (%( - 5==/= ' ( +'$ =6* INT0 (P3.2) and INT1 (P3.3) #7 $ #7 ! ( E% ( % =6* 2' + % ( ( % % C$(' ( D '%%( - # (% '%" C$('D % (+ + % ( % %%$" - ' ( ('& ' %'(+(' +(!$ '( ( '$ & (% '( (% $( $ & '('( $%(- + =6* # $ ' ' -$ Table 9 % % '( ( '$ & - ' ( ' " (+ ( + % ( % %%$ 6 XR88C681 #7 B , > ><81>1 ) 1 1 #7 B > 92 6 > , = 6 $$%% '$( 9-(' . 8051 CPU #% XR88C681 Figure 5. An Approach to Interfacing the XR88C681 DUART to the 8051 Microcontroller '('(& % $ Figure 5 $ + '( % +% $( - E%$ ( $(' E%% ( + , & %%( - (% '( #7 ( (% ( '% #7 ( ( , - B (% % =6 , ( +( (% !'( - (% ' ( %'( " $ ( ' - ' ( %(' ( # '% + Figure 5" %( ' H% #7 ( (% ($ #7 ( + * " -( ( - + ( %(' ( ( '$ ( 18 ( '$ & =6 , $% (%% # '3 $- %(- '3 # ( M% -( '%%( - - H% ( %(' / ( ' , % (( $ '%% + ( E%" H% #7 ( ( -$ - C(-D $ , ( + ( %(' ( $ % ( C.6.1.2 8080A Microprocessor == (''%% (% + ( %( + # '%%% # - " ( (% =( (''%% E(% A6;" 6;" $ A; %(% $$(( &" (% (''%% E(% '(%" ( $ ' C'D , $ &('&" % $('% $ =< '3 0 $ == &% =< XR88C681 '3 0 (% % %( + ' $(( ( - $ - ( - '%%& (( - %' + == , " + ! '&% == &% (% % %( + ++( - ($('( *% $$(( &" %( ' == , $(' $% $('& ($ ' % %(- %" == (' (% % %( + %( - %(- ( - ( +( " + == $('" ( +( - *% %(- %L ( $ ''%% & $ ( $('% #7 # '3 $- 2 & $ 2B & B( # # , $ #B , B( Figure 6 % % %'(' + == , $ 07 A6; 6; A; 8080A CPU 6 89 #7 #72 B *#7 89 1 < 6 / > 7: ,8# 9 G#7 1 < 6 8228 System / Controller > #7 2 2B # #B 2#7 A; A6; 07 8224 Clock Generator B # 2 G 22 G7 07 *2 A6; * 27 Figure 6. Schematic of 8080A CPU Module 8080A CPU Module Interrupt Structure C# 'D + == , (% $%'($ == , $(' ' %(%% + %(- %4 #72 $ #7 $$(( &" == *(('( *% ' %(%% + %( - %(- " #7 #72 (% '((- # 2 " $ #7 (% '((- # E% ( #+ C2 # D ' $ % ( 3$" #72 > ( C(-D ( $('( - == , ( ( E%% + (% B #7 ( (% %%$ & ( $(' E%( - ( " , ( ' (% ' ( %'( + '( + (% ( %'( " , $ ( %% #7 ( == *(('( *% ( & --( - #7 CD #7 (% '( C# '3 $-D %(- , $ % ( XR88C681 $ ( (( '%% + ( %('( - == , $ & %% C! D '$( '%%( - 8 '" #7 (% %%$" , $ (% (( - C'D ( +( % # '% + == , $" (% C'D ( +( (% &('& '$ + + 2 ( %'( % == , %% (- $(++ ( %'( % - > % ( %'( % & '% %'(+(' '( % (( , H% & %'" ( ( %(' ( !(%% Table 10 % % (% + % 2 ( %'( %" '$%" $ '% $( 2 $$%% Op-Code (hex) > > 2> 2 > Mnemonic 1 < 6 / > Restart Address (hex) = = = 1 1= Interfacing the 8080 CPU Module to the XR88C681 DUART for Interrupt Processing == , ' ' '$ 5==/= $ ( # ( $ Figure 7 % % ' ' ($ ( +'( - 5==/= == , + C! D '$ ( '%%( - Please note that (- = only includes information pertaining to DUART interrupt servicing. '('(& %' % =< '3 0 " $$%% *%" ' ($ + %'(' # (% %'('" # (' ( (% '$ / ( & $$(( &" % ' +(-$ ( #$ + '( $%'(( + (% '('( (% % $ 5==/= ( E% ( == , " & --( - (% #7 CD (% %(- (% ( $ $ ($ '((- #7 ( + , ' == , % '$ (% ' ( %'( " ( ( %% '( #7 %(- + == *(('( *% ( (% (" #7 %(- + $ #7 %(- + == ' -(' CD #7 $ #7 %(- % $ ( - 8 '" #7 $ #7 -(' CD" + - ( % -(' CD" $ & %%( - + 2 2 ( % + 7><9<< *% ++ 1 (% C( -D + #7 $ #7 %(- % (% %$ ( % & ( $(' E%( - ( (% '(% %(' -" % %( %%$ #7 %(- ' 2 ( % + 1 %%$" $" ($ ( + (% $(' 1 ( + (% $('" $ > ( % + == $(' Please note that, in this example, the value "E716 " is hard-wired into the input of U3 (% (% '$ + C '" ' (% $ (% -$ ( , $" ( $ %" , ( $ / ( (% ,- $ ' - ' '( # (' ( + !(%% (% '( ( & Table 10. 8080A and 8085 CPU Restart Instructions Used With Vectored Interrupts +" ' , '(% '$ + + % 2 ( %'( %" ( ( -( !'( - (% ( %'( & $( - ,- ( ( C% $$%%D +$%" - ' ( '$ C% $$%%D '( 2!4 #+ '$ C2>/D (% $$ *% $( #7 '&'" (% '$ '% $% ( C $" , ( $ / ( ,- $ - ' ( ' '( ( & % Table 10 = XR88C681 U1 #72 #7 / 6 ;'' U4 #7 ;'' *#7 8080A CPU 1 < 6 / > 8228 Bi-Directional BUS Driver U2 U3 2 2 1 < 6 / > # # # #1 #< #6 #/ #> XR88C681 DUART 7><9<< #7 Figure 7. Circuit Schematic depicting approach to Interface the XR88C681 DUART to the 8080A CPU, for "External" Vectored Interrupt Processing (Interrupt Service Routine resides at 002016 in Memory) ( ' == , ' % = $(++ ( %'( %" ( ' % = $(++ ( $( ( $('% (% ' '($ & ('( - '" % $ ( Figure 7" $ & $(( - '$% + ' + 2 ( %'( % ( % + *++% % Table 10 % *++% %$ $ & $( - #7 '&'" $ & ( %%'($ ( E%$ ( %(' C.6.1.3 8085 Microprocessor ==6 , (% & # (''%%" - ( (% $ '$ == , + $ ' % $ ( %(( + == ==6 ( '$ '( ( - '3 0 + '( % + =< , '(" $$( - %3 ( E%" $$( - 1 C$('D ( E% ( ( %" $ $$( - % + + ( ((& ==6 %( E(% % - -(' ( $ $' *% %(- % (" #" #B" 2" 2B " ( $ ( ((I ( ' " ==6 ' ( % (!$ $$%%. *% > '(+('&" = (% + $$%% *% % ( % ( = ( *% 8 '" ><91>1 =( ' (% $$ ( $ $(! $$%% $ %% XR88C681 Figure 8 % % %'(' + ==6 , $ 1 < 6 / > 1 < 6 / > = 92 = 1 < 6 74LS373 = 1 < 6 ) ) 1) <) 6) /) >) =) 1 < 6 / > 1 < 6 / > 5 5 , >6 /6 66 #7 #7 # 2 #B 2B #. B 8085 CPU Figure 8. A Schematic of the 8085 CPU Module Figure 9 (%% ' ( +'( - 5==/= ==6 , $ 7 5==/= " ( (% '%" (% & $ -" %(- % 2 $ 2B + , $ ' '$ $ B ( % + 1 8" % '$ M% % %(& ' '$ 5==/= $(' , $H% #. -" %(- # $ #B + , $ ' '$ $ B ( % + " %'(& XR88C681 > 1 . > 1 = 5 5 , >6 /6 66 #7 92 74LS373 ) =) < > = 6 Address Decoder #7 = 6 B 2 XR88C681 2B .82.# #. B 8085 CPU Figure 9. Schematic of the XR88C681 Interface to the 8085 CPU Module (Memory Mapped). H% #7 ( % $(& ($ + Figure 9" '% (% % ( $$%%$ ( Figure 10 $ Figure 11 8085 CPU Module Interrupt Structure ==6 , %% (' $ C2! D ;'$ # '%%( - ==6 % < %3 ( E% ( % 66" /6" >6" $ #7" $ %3 ( E% ( 1 , B $(%'%%( - ( +'( - + ( %('( - + ( $('% %' % " & ' ' $ ( %3 ( E% ( % + + %3 ( E% ( %L + % ( % % C(' # D '%%( - ( ( - ( E% %% C2! ;'$ # D '%%( - Table 11 (%% % # E% ( % $ ( ''(%('%.+% XR88C681 Input Name >6 /6 66 #7 Trigger ,%(( 2$- (--$ 8(- 9 ( $ 8(- 9 ( $ 8(- 9 ( $ Priority 1 < 6 Type (' (' (' 2! ;'$ Acknowledge Signal? 7 7 7 #7 J C9D Address (Hex) 1 1< Table 10 Table 11. 8085 CPU Maskable Interrupt Request Inputs and their Features Direct Interrupts ==6 , ( % >6" /6" $ 66 C(' # D E% ( % '(+('&" (+ & + % ( % %%$" - ' + , (%" '( + ' ( %'( " ('& $$ ( & '( $( $ & '('(& (( ==6 $('" $ '% - ' '( % C('D ( % $ ($ ( $(' ( & % + C# '3 $-D 8 '" ''$( - Table 11" (+ >6 ( %%$" C1/D $ $$ ( - ' + , " $ - ' $ ' '( ( & % (% % %( ( % '' ( %(' ( -( % '( ( & ==6 , ++% ( (((I( " (( % + %3 # % (% ((& (% +'$ Table 11 # %$ $ % ((& % & & C $( -D ( E% ' (' ( % C+ ED $ (% ( - %('$ & , " (% (((I( %' - (% (' ( %E &" ( (% %%( 66 ( E% '$ C( D ( %(' ( + (- ((& >6 ( E% +" % % -$ -( % (% ( (%. +( Table 11 % ( $('% ==6 , ( % C! D '$ ( % $ ' $% %$ ( ! '$ ( '%%( - ($ (' % $ + == , % Section C.6.1.2 Figure 10 $ Figure 11 % $(++ '% ' %$ ( +' 5==/= ==6 , Figure 10 % % %'(' ( E% C('D /6 # ==6 , # (% '%" # (' ( + % -( 1 %&% & (% (% & %( ( +' ' (E" '% (% C# '3 $-D %(- $ ( +' 1 XR88C681 ;'' /6 > #7 > 92 ) > < 1 74LS373 6 = $$%% '$( 9-(' # #. B #B 2B 8085 CPU XR88C681 2 B Figure 10. The XR88C681/8085 CPU Interface for Direct Interrupt Processing (Interrupt Service Routine is located at 003416 in System Memory) Figure 11 % % %'(' ( E% C2! ;'$D # ==6 , # (% '%" # (' ( + % -( / ( %&% & 11 XR88C681 ;'' U1 #7 #7 U4 6 #7 / ;'' 8085 CPU 1 < 6 / > 1 < 6 / > 1 2 2 1 < 6 / > # # # #1 #< #6 #/ #> XR88C681 92 1 < 6 / > = ) ) 1) <) 6) /) >) =) SN74LS244 1 < 6 / > 74LS373 Figure 11. The XR88C681/8085 CPU Interface for Vectored Interrupt Processing (Interrupt Service Routine is located at 002016 in system memory) C.6.1.4 68HC11 Microcontroller +'% +(& + ('' %" +$ % /=8 ('' % (% +(& + ('' % ++% % + +( - ((%4 6 ( '( , ,% 2, . 1< XR88C681 Figure 12 % % '3 $(- + /=8* * 5 9 25 9 2 #) 5#) 22 $ %'( '3 9-(' # 9-(' 6/ *&% , ;8 ( &% *% 2! %( $$%% ;9 $$%%. ,# P : # # $ 8 $%3 , #. # 5 5 . = , , * , , , 2 Figure 12. Block Diagram of the MC68HC11 Microcontroller /=8 ' ' +(-$ ( C( - (D $ ( C2! $$ (!$ *%D $ #+ $(' (% ' +(-$ ( C( - (D $" ( /<: &% + $$%% %' (% ( * # Please note that this does not mean that there is 64K bytes of memory, or other addressable portions within the device /=8 ' +(-$ + C( - (D $ ( ' $$%% & ' % ! +" (+ % $%($ ( +' (% * " * % ( C2! $$(!$D $ /=8 (% 16 ' +(-$ ( 2! $$ (!$ $ & &( $ * ( ;''" $ %( $(' /=8 ' %(%% + 6 $(++ (+ '( % 2' + % % (+& $(%'%%$ Port A , ' %(%% + 1 ( ( %" < ( % $ ($('( ( (% (% %$ % ( &% + ( ( % ' %$ + ,% XR88C681 '' + ( ( % % ( ' + '( %L $ + + ( % % ' + '( % Port B , * ' %(%% + = ( % #+ /=8 * (% ( - ( %( - '( $" (% + '( % % - % 8" (+ /=8 (% ( - ( ! $$(!$ $" (% ( + '( % $$%% & + &.( $(' ( +'( - = 6 Port C , ' %(%% + = ($('( ( % B /=8 (% ( - ( %( -'( $" (% + '( % % - % ($('( 8" (+ /=8 (% ( - ( ! $$(!$ $ (% ( + '( % (!$ $$%%.$ % > '(+('&" $( - +(% + + & '&'" (% ( + '( % $$%% & , * (% $$%% & + $$%%( & $('% $ ( ' % ( - %' $ + + & '&'" (% ( + '( % ($('( $ % (% ' $(!$ ( % + $$%% ( $ ><91>1 ' $(' Port D , ' %(%% + = ($('( ( % 8" (% ' ' +(-$ % '( ( ,( # +' ,#" $ ( ('( % # +' # Port E , 2 ' %(%% + ( < = ( % $ $( - '3-( - ( (% ' ' +(-$ + '( % - % ( % ( % '( . ' % ( % ( + ( +'( - 5==/= $(' + % ( % $(%'%%$ IRQ (% (% C%3D ( E% ( #+ (% ( (% %%$ -" --$ CD" /=8 * ( ' - ' " 1 ( %&% & '( % (% % %( + ( %( - ( ( %(' ( %($% (% '( ( & AS/STRA C $$%% D ' %$ $(! $$%%.$ % + , (% ( (% -(' C(-D $( - +(% + + & '&'L $ -(' CD $( - %' $ + + & '&' #+ /=8 (% ( $$ ( ! $$(!$ $ $ ( +' 6/ &% + $$%% & %'" ,% * $ E($ % % ( Figure 13 Figure 13 % (%% 5==/= '$ ' '$ /=8 * + ( $( ( #+ E%% ( " (% '( #7 ( ( %%$ -- " (' (" ( " '% #) ( + , %%$ B (% ''% * ( ' ( !'( - (% ' ( %'( + '( + (% ( %'( " - ' ( %(+ '( " 1 ( %&% & % (% % %( ( % H% ( %(' ( %($% (% '( ( & * ( (%% ( '3 $- %(- # %$" * ( M% '%%% - ( %(' ( ' * % (( $ '%% + H% ( E%" #7 ( ( -$ $ * ( + # (' ( $ % '%%( - ( %$ ( $ Figure 13 --(' '('(& E($ - B" " $ 22 %(- % + " + .B" 22" $ 2 ''3 % $ ( Figure 2 (% '('(& % % ( '$$ ( Figure 14 1/ XR88C681 6; 2 * .B = 6 $$%% '$ B #) < > #7 #% 0 ) 1 74HC373 1 > > 68HC11 XR88C681 Figure 13. XR88C681/MC68HC11 Microcontroller Interfacing Approach 1> XR88C681 .B B 2 ''3 22 22 Figure 14. Glue Logic Circuitry Required to Interface the MC68HC11* C to the XR88C681 DUART C.6.1.5 Z-80 CPU ?= , ' ( +'$ ( - ( #$" (+ ( , (% ( - ( # $% 8" + %3 + C'%% ' ( (&D" $(% %%'($ ( ?= , ( % $ ( Section C.6.2.1 C.6.2 Z-Mode Interrupt Servicing ( ( #$ +( - $ % + # % % ( 3 C ?$D ' $ % Table 3" ( $ ' $ ( ?$ # - " , ( +'( - ( - ( ?$ ( + '( % +% $( - ( %('( - #+ E%% ( %('( - + , " ( ( %% #7 ( -" -- CD ' , % $'$ ( E%" ( ( (%% # : # '3 $- %(- '3 B , % $% # : %(- ( (% ( +( - (% ( E% (% 1= %$ B % '($ $'$ # : %(- " ( (" ( % %" ' ' % + # ;' -(% #; *% , ( $ (% C( 'D ( +( L $ $( +( - ( -% %$ C( 'D ( +( %' + ( E% -" (' ( $% %(' ( '( + ( %(' ( +$%" -' ( '$ '( + ( %(' ( ''(%(' + ?$ ( (% ( % % (((I ( E%% + % ( $('%" ( $ % 9 % %% % $('%L $ ' + % $('% ' +(-$ ( ?$ % '$ (((I ( E% + ' + % $('% & ' '( % $('% ( C$(%&'( D ( % % $ ( Figure 15 XR88C681 ; #7 #7 ; #2# #2 #2# #7 #2 #2# #7 #2 #2# #7 #2 CPU # : # : # : # : # : 8#082 ,##G 9B2 Figure 15. A Diagram of Numerous DUARTs Configured in an Interrupt Daisy Chain (for Z-Mode Operation) # $$(( #7 $ # : ( %" ?$ % %% #2# $ #2 ( %L (' $+( $ % +%4 IEI - Interrupt Enable Input (% '((- ( (% & ( (+ (% ' +(-$ ( ?$ #+ (% ( (% -(' C(-D %3$ ( E%%" + (% " $ Note: Those interrupts which have been masked out by the IMR are still disabled. However, if this input is at a logic "low", then all interrupts (whether masked or unmasked) are disabled. Hence, IEI can act to globally disable all DUART interrupt requests. ( " E%$ & $('" % M% %('$ #+ & + % ' $(( % +%" #2 ( ( -(' CD Note: Once the IEO pin has toggled "low", and the CPU has acknowledged the interrupt request and has completed the interrupt service routine, the IEO pin will remain "low" until the user invokes the "RESET IUS" command (see Table 3). Therefore, if the DUART is going to operate in the Z-Mode, the user must include the "RESET IUS" Command at the very end of the DUART interrupt service routine. System Level Application of the IEI and IEO pins Figure 15 $('% %(% + % ' '$ ( $(%&'( +%( # (% +(-" +% % (-% ( ((& (% (% '% (% H% #2# ( (% $($ ;'' +" %3$ ( E%%" + (% &% $ $('" '$ M% (- + C(-% ( ((&D $(' (% + ( ((& (% (% '% #2# ( + (% ((& $(' (% ' '$ #2 + (-% ((& B C(-% ((&D $(' E%% ( " (% #2 ( -- CD (% ( ( " $(% C ((&D $(' IEO - Interrupt Enable Output (% '((- (% & ( (+ (% ' +(-$ ( ?$ (% (% + (% ' '$ #2# ( + ((& $(' (% (% C(-D (+ + +( ' $(( % $('H% #2# ( (% -(' C(-D $(' (% E%( - ( + , 1 XR88C681 + (%%( - & ( E%% , (% C ((&D ( (($ + (%%( ( % ( #2 ( + C(-% ((&D % --$ C(-D +( -" ' -( " Figure 15" + (- $(' (%" (% ( ((& (- % % %( ((& '% (% C( E%D '((& ' $(%$ & '( % + & + % + Figure 16 % % (( - $(- $('( - %E ' + % ( '' $( - $ +( - # E% + #7 # : > #2# 9 7 ; 9# ;2 9 #2 % # $ Figure 16. Timing Diagram Illustrating the Sequence of Events Occurring Between the DUART and the CPU During an Interrupt Request/Acknowledge and Servicing Additional Things to Note About Z-Mode Operation ?$ ( (% %$ & ?(- ,( ' % ?(- ,( ' % # ;' -(%" # '3 $- # : ( " #2# ( " $ #2 +" Figure 15 '$ %(& ( '$$ % ( ' %" ( $$(( ( ( + % % ( $ (" ?$ ( (% ' $$ (+ (% ( +'$ +( '%%% ?= (''%% # $ ===* < ==/* , ==/ =6=/* , Please note that it is possible to interface the 80X86 Family of microprocessors to an I-Mode DUART, however, additional components and design complexity would be required in order to accomplish this ' (E.'% ( +'( - ?$ % (''%%% (% % $ ( $(" ( +( - %'( % C.6.2.1 Z-80 Microprocessor ?=* , ' %(%% + = ( *%" / ( $$%% *% $ % ' ( % ?=* , (% & +!( '%% (' ' '& ( +' ( ?$ #$ $(' (% (% '% XR88C681 ?=* , ' ' +(-$ ( + $(++ C( $%D ?= (% % ( ( %% '('$ ( +' % + * ,.* % 1 < 6 ,8# < 1 6 1 < 6 / > = Z80 CPU (%& ( $ '% (% $$%% $ $ % (!$ Figure 17 % % %'(' + ( + ?=* , < 1 1= = 1> > 1/ / 16 6 1< < 11 1 1 1 1 07 = 8 > / 22 6 * ) < B # 1 * : B / ; > 1 < 6 #7 / 7# > 8 9 = 2) #) Figure 17. Pin Out of the Z80 CPU Device ?= , ( % $.B( ( % & $ #. ?= $% E( % $$(( - -(' ( $ ( +' $('& & $ ( $('% ( % '" ?= , $(' $% ' ( ' % %(- %4 2 & $" 2B & B(" # #. , $" #B #. , B( # :.#7 # '3 $- ( % 2' + % + '( % ' $($ + " B" #)" 2) $ ( % Figure 18 % % %'(' + ?= , $" (' %% ' ' !' ' % %(- % + % , ' ( % < XR88C681 07 A6; 6 '3 ( ,8# > #7 7# B # * ) 8 9 8 * : B 2) #B #) # #7 2B 2 22 Figure 18. Schematic of Z-80 CPU Module Z-80 CPU Interrupt Servicing Capability ?= , ' ( % ( E% ( %4 7# $ #7 7# (% C7 %3D ( E% ( ( L $ #7 (% C%3D ( E% ( ( %3 + ( +'( - " & ' ' $ ( #7 ( ?= , ' ' +(-$ ( + $(++ ( $%4 2! ;'$ (' C,(D ;'$ < 2' + % ( $% % #7 ( + ?= , $ ( $(%'%%$ ( +( - %'( % External Vectored Interrupt Processing (Interrupt Mode 0) ?= * , ( ( (% ( $ (+ C# D ( %'( % !'$ B #7 ( (% %%$ & ( $(' E%( - ( " , ( ' (% ' ( %'( + '( + (% ( %'( " , $ ( %% #7 -- CD #7 (% '( C# '3 $-D %(- , $ % ( $ ( (( '%% + ( %('( - B ?= , % ( # $ " ( (% XR88C681 (( - C' ( +( D *%" +( %%( + #7 # (% '% + (% ( $" (% C'D ( +( (% '$ + + 2 ( %'( % ?= , %% (- $(++ ( %'( % 1=8 % ( %'( % & '% %'(+(' '( % (( , H% & %'" ( # %(' ( %($% Table 12 % % (% + % 2 ( %'( %" '$% $ '% $( - 2 $$%%% Op-Code (hex) > > 2> 2 > Mnemonic = = 8 =8 18 1=8 Restart Address (hex) = = = 1 1= (% ( - ( #$ $ ?= (% ( - ( # $ Direct Interrupt Processing (Interrupt Mode 1) ?= * , ( ( (% ( $ (+ C# D ( %'( % !'$ B #7 ( (% %%$ & ( $(' E%( - ( " , ( ' (% ' ( %'( +$%" - ' ( ('& $$ ( & '( $( $ & '('( $%(- + ?= , $(' $ - ' ( '$ '( ( %&% & # (% '%" - ' $ ' 1=/ ( & % (% % %( + ( %( - ( ( %(' ( (% (' '( ( & ?= , $ $% ($ ( $(' ( & % + C# '3 $-D , M% '%%% - # (' ( " (( % '%% + ( E% $ % ( Peripheral Vectored Interrupt Processing (Interrupt Mode 2) ?= * , ( ( (% ( $ (+ C# D ( %'( % !'$ (% ( C$D (% & %+ (+ % (%% ' ' ( E% % + % (% #7 ( + ?= , (% ( $ % ( ( - $(' ($ (+& (%+ '( (" M% ( ( %('( - B #7 ( (% %%$ & ( $(' E%( - ( " , ( ' ( ' (% ' ( %'( ' (% ' ( %'( (% '$" , $ ( %% #7 %(- ( + ( $(' ( %(' (% -( ' ( ( - ( $(' % $'$ #7 %" ( ( ' C( 'D *% (% ( ' ( $ & , $ , ( ' - ' '( +$ & ( ' Please note that if the IEI input to the DUART (or Zilog peripheral device) is "low" then the DUART (or Zilog peripheral device) will be disabled from generating any interrupt requests to the CPU ! + (% ' (% % $ Figure 19 # (% '% 5==/= (% ' +(-$ ( ?$ $ (% ( +'$ ?= , B E(% ( %('( -" ( ( %% (% Table 12. Z-80 CPU Restart Instructions Used with Vectored Interrupts +" ' , '(% '$ + + % 2 ( %'( %" ( ( -( !'( - (% ( %'( & $( - ,- ( ( C%D $$%% +$%" - ' ( '$ C% $$%%D '( 2!4 #+ '$ 2>/ (% $$ *% $( - #7 '&'" (% '$ '% $% ( 8 ( %'( $" , ( $ / ( - ' $ - ' ( ' '( ( & % Table 12 % (% % %( + ( %( - ( %(' ( -( % (% '( ( & ! + '('( (I( - (% + + ( '%%( -" ( ( +'( - " (% % $ ( Section C.6.1.2 (% %'( $(%'%%% ( +'( - == , $ (% !' % ' '$ %$ ( ?= , " ($ <1 XR88C681 (% '( (" ( " '% #7 ( + , %%$ ' , % '$ (% ' ( %'( " , $ ( %% #7 %(- (% ( ( %% # : # '3 $- ( % + %%$ # : %(- (% ( + & ! '&' ( C# :D C# Most Significant Byte Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 % + # -(% (( , #7 '3 $-D '&' " ( % % # : %(- " ( ' ' % + # ;' -(% #; *% (% $ ( $ & , " $ - ' ( '$ ( ( %(' ( # '% + ?= , " (% '( (% / ( $$%% (' (% $( $ + Table 13 Least Significant Byte Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 > % (- (+(' *(% (( # ;' -(% + Note: The LSB of the IVR is always set to "0" once read by the CPU. Interrupt Service Routines must begin at even ddresses. Table 13. The Relationship between the Contents of the Interrupt Vector Register (of the DUART) and the location of the Interrupt Service Routine (Z-80 CPU) $$(( &" % % + ' % .% $% ( # -(% + , " $( - ( + ;'' (- ((& ( 6 $$%% '$ ('(& ((& ( . 1 #2# #2 1 > #7 > #7 B 2) #) Z80 CPU 2B 2 B #7 # : XR88C681 Figure 19. Schematic of an Approach to Interface the DUART to the Z-80 CPU (for Z-Mode Operation) << XR88C681 C.6.2.2 8086 Microprocessor ==/ (''%% (% / ( (''%% +'$ & # ( Figure 20 % % ( $(- + (% # Please note that in (- , pins 24 - 31 have some additional labels, located off to the right of the package. These additional labels will be explained later in this text. 07 < 1 = > / 6 < 1 7# #7 9: 07 1 < 6 / > = 1 < 6 / > = 8086 CPU < 1 1= 1> 1/ 16 1< 11 1 1 1 = > / 6 < 1 ; 6 /.1 >.< =.6 ./ *82.> 7.5 ).0 ).0 9: ) ) 2 2 G 22 89 89 B .# . 27 92 #7 Figure 20. Pin Out of the 8086 Microprocessor Device # - -% 3 ( ' + (% # & (!( - + '( % + & + % ( % (% $(' ' %(%% + / ( *% $ ( $$%% *% *% (% (!$ ( / $$%% *(% 6 + 6 $$%% <6 *(% / (!$ ( %% (% 1 / + /.1" >.<" =.6 $ ./ + % ( % $$%% ( % $( - +(% + + & '&' 8" $( - %' $ + + & '&'" % ( % 3 ( + '( % XR88C681 -" 6 '% 6" /.1 ./ '% 1 / %' $ - + (!$ ( % (% ' $ & 7.5 ( ( B (% ( (% (-" C( D $ (% %'$ $ ( % < - 1 3 ' $+( (( % % $ 7.5 J ' ( Table 14 B ==/* , % ( (% $" ( % % ' % & %(( + ==6* ," $ E(% & $$%% ' $ ''3 - + , $ Pin Number < 6 / > = 1 1 MN/MX = 1 (Min Mode) 89 89 B MN/MX = 0 (Max Mode) ).0 ).0 9: .# . 27 92 #7 ) ) Table 14. MN/MX Mode and Function of Pins 24-31 of 8086 CPU Device. B 7.5 (% " ==/* , (% ( - ( C!D $ (% $ (% ( $$ + '! ('( % ( (' ==/* , E(% % + ==> (' $ '%% 7, # (% $" %'( % ' === (% E($ - & $ #. ' % %(- % ==/* , ' ( % ( E% ( %4 #7 $ 7# 7# (% '((- C %3D ( S2 S1 S0 E% ( L $ #7 (% C%3D ( E% ( #+ ==/* , (% ( - ( C( D $" #7 # '3 $- ( (% ( ,( < % Figure 20 8" (+ ==/* , (% ( - ( C!D $" #7 %(- % $($ + " " $ ( % ( === % ' Table 15 % % '%% %% $ === '( % %$ " " $ C!D $ %% %(- % Processor State # '3 $- $ #. , B( #. , 8 $ ''%% $ & B( & ,%%( 8288 Active Output #7 # #B 7 B 7 Table 15. 8086 Processor State/8288 Bus Controller Active Output as a function of S0, S1 and S2 XR88C681 Figure 21 $ Figure 22 % ==/ , $" ( - ( C( D $ C!D $%" %'(& > > #7 #7 = 6 89 C 74LS373 ) > = 6 92 C 74LS373 27 . ) = 6 # .# ;'' 7.5 B 8086 CPU 2 #B 2B Figure 21. Schematic of the 8086 CPU Mode (Min Mode) <> XR88C681 9: 9: 27 . 92 #7 > B # #B #7 2 2B # #B 8288 Bus Controller > ) > 74LS373 = 6 = 6 8086 CPU 7.5 74LS373 ) = 6 Figure 22. Schematic of the 8086 CPU Mode (Max Mode) 8086* C Interrupt Processing #+ ( ' E(% ( %(' + , " ( ( %% , H% #7 ( & --( - ( (- ' , % '$ (% ' ( %'( " ( ( %% #7 ( (+ ( - ( C( D $ % " " $ ( % CD % Table 15 # ( '%" # : ( + ( ( %%$ ' (% %" ( ( ( (% !'$ ' C( 'D & > + $ % ==/* , ( $ (% $ $ (& (% & < ( $ <= $( '( + ( %(' ( ( & ( ' (% C( 'D (% = (% ($" ==/ * , ' ''$ 6/ $(++ ( '% 66 $$(( &" %( ' ' ' (% (($ & C %.@ Figure 23 % % %'(' + 5==/= ( +'( - C( D $ ==/ , $(' Please note that the DUART has been configured to operate in the Z-Mode. Therefore, the user must account for the IEI input to the DUART device XR88C681 > > 74LS373 D C Q < > = 6 74LS373 D Q = 6 $$%% '$ 1 > 1 = 6 89 92 C 27 . #7 #7 + (- ((& $(' .# # : #7 #2# ;'' 7.5 2 2B B XR88C681 B 8086 CPU Figure 23. Schematic of the XR88C681 DUART Device Interfacing to a "Min" Mode 8086 CPU Device D. TIMING CONTROL BLOCK (( - *'3 % % %'(+& ( % .% (%% %( $ '( $ ' ' (( - *'3 ' %(%% + +( - %4 %'( ('( *( 0 < / ( .( < 2! # ,( % ''3 %(% $ '(%" $('& '3 ' -(%% 14 5% Figure 24 % % '3 $(- + (( - '3 + 5==/= $(' XR88C681 #,< 5 #,1 5 ,% -(%% " 9 5 5* #, (($ & / N. ( 14 5 ! 14 5 ! (($ & / 14 5 !* 5.9: 5 %'( ('( *( 0 14 5 #,6 5* #, 5* !* N>O Figure 24. Block Diagram of DUART Timing Control Block 2' + (( - *'3 (% $(%'%%$ 4 D.1 Oscillator Circuit: '&% %'( (% &('& ' '$ ! & '%% 5.9: $ 5 ( % %'( ('( (( '( + '( % % $ + % '&% %'(" $ ++% %( - %'(( - %(- " + % & *( 0 " $ .( '&% 9 %(- +E '& + 8I $ < 8I (% E($ + ( + 8" '&% 9 %(- +E '& + 1/=/< 8I (% E($ + - ( + % $$ ( % & *( 0 Table 18 Figure 25 % % ' $$ %'(' + 5 9 %'( '('(& 6 XR88C681 4 A & Q 6 4 A & Q 6 4 4 5 XR88C681 1/=/<8I , % &% 5 Figure 25. A Recommended Schematic for the XTAL Oscillator Circuitry Note: The user also has an option to drive the Oscillator Circuit with a TTL input signal, in lieu of using a crystal oscillator. If this approach is used, the TTL must be driven into the X1/CLK pin, and the X2 pin must be left floating. #+ % $%(% % % + %( - '&% %'(" Figure 26 % % ' $ '%%& '('(& ''(% (% M'( XR88C681 5 5 G 1/=<8I 5 ( % + % ><8< Figure 26. A Recommended Schematic to Drive Multiple DUARTs From the Same Crystal Oscillator. Note: The user is urged not to use the 74LS14 Schmitt Trigger Inverter in lieu of the 74HC14 device. The input of the 74LS14 tends to load down the oscillating signal from the DUART, to the point that the Schmitt Trigger inverter can no longer change state or respond to the oscillator signal. 6 XR88C681 D.2 Bit Rate Generator *0 *( 0 ''% (( - + %'( ('( $ - ''3 %(- + 1 ' & %$ $ ' ('( ( % -( + 6 % 63% Please note that the BRG will only generate these standard bit rates if the Oscillator Circuit is running at 3.6864 MHz $$(( &" ' ''3 +E '(% + *0 / (% % % % ' %' + $(++ %% + ( %" - $ + *0 (% %'( (% $ & %( - '( - N>O (%( - + % %% + *( %" + *0" (% % $ ( $(%'%%( + '3 ' -(%% % ( Section D.5 '3 $(- + *0 '('(& (% % $ ( Figure 27 N>4 5 N14O N>O 14 5 5.9: 5 5 %'( ('( *( 0 % $ * *N>4 5* *N14O 14 5 5* Figure 27. Block Diagram of the Bit Rate Generator portion of the Timing Control Block 6 XR88C681 D.3 Counter/Timer (( - *'3 % ' ( % / ( .( . . (% - / ( $ ' (' ' % + % (( %'% % (% ( Figure 28 % % '3 $(- + '('(& % $( - . %'( + % (( - %'% + .( ' $ & (( - ( $ N/4 %( .( $" (( - ' $ N/4 %(% $ '(% %'( ('( ,% -(%% " 9 (($ & / 14 5% #, (($ & / 5 5* .( ..G ,1 N Bit 6 Bit 5 Bit 4 C/T Mode ( ( ( ( Timing Source 2! # #, 5 5 '3 + %( 5* 5 '3 + * %( 5.9: # (($$ & / 2! # #, 2! # #," (($$ & / 5.9: # 5.9: # (($$ & / Table 16. ACR[6:4] Bit Field Definition - C/T 61 XR88C681 D.3.1 Timer Mode: Please note that of the two C/T Modes, the Timer Mode is the only mode which is relevant to the function of Bit Rate Selection. 8" + ' %%" $ (% % $(%'%%$ # ( $" . '% % - $(($ $ - % %E % ($ (% (' ( ''3 ($% + ' % + .( -(%%" $ 9 . ' %$ % - ( - ( $ $' /5 ''3 + & ( ($$ & *0 %E" (-( ( - + . (% , ( " ,1 #+ . (% -$ ( ( $" +E '& + %( - . %E ' !%%$ % +%4 . E '& J E '& + '$ (( - ' RN OR = + N9O B4 N O J ' % + -(% ( $'( + N O J ' % + 9 -(% ( $'( + ( ' . (% $$ % /5 ''3 %(- & '('(&" %( - ( (% ./ +E '& + . %(- +" ( " $($ + . ' !%%$ % +%4 *( J E '& + '$ (( - ' 1RN OR = + N9O ' % + $ 9 -(%% & ' -$ & (" ( & -( 3 ++' ! + '&' + %E . -( % ( %( - % ( .9 '( + $$%%(-- C 72D ' $ Table 1 . % ' ( %& %%E C 72D ' $ '%% . ( ' (( - '&' $ -( (( - '&' %( ' % %$ ( $ 9 72 2 G %% (" ( # % -(% #N1O" (% % ' ' '&' + %E (% % % + . % ($(' 6< ( - " (+ ' $(( (% -$ - ( ( ( %3 -(% # #N1O ' '$ & (%%( - $$%%(--$ C, 72D ' $ Table 1 # #2 $" " ' $ $% '& % . D.3.2 COUNTER MODE # $" . ' % $ + %% ( ( .9" -( ( - '( + C 72D ' $ 72.2 G %% ( #N1O (% % '( - ' + / . ( ' ( ' % / $ $+ ( ! ' ( / ( ( (% %$ & , ( C, 72D ' $ #+ ,1 (% -$ + ." ( ( (- ( ( ' (% '$" (' ( -% # % (- % $ #N1O (% '$ . (% %$ ( C, 72D ' $ C 72D ' $ ( ' (% ( - %% ' ( % ( .9 , & ' - ' % + 9 & ( ' 3% ++' & + %%E 72 ' $ #+ % -$ (% % %$ $ %$ + ! '&' D.4 External Inputs % + % + # , ( % #, #,6 %$ % $(' ! ( % (( *'3 % (( - %'% + %(% $ '(% + ' % Please note that the user can specify whether a clock signal, applied to one of these external inputs, is a 1X or a 16X clock signal; via the Clock Select Registers % Section D.5. $($ $(%'%%( # , ( % $ ( + '( " % % Section E D.5 Clock Select Registers, CSRA and CSRB # Figure 24" '3 ' -(%% 14 5H% '3 ' -(%% % % ' %' (' ''3 %(- % ( $( %(% $ '(% + ' % % % %' 1 $(++ % $$ ( % + *0" .( " % ! ( % (( - %' + %(% XR88C681 $ '(% Table 17 $ Table 18 % ( %( ' % + % $ ''3 %' $(( - %(% $ '(% Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 '( '3 ' Table 18 %( '3 ' Table 18 Table 17. Bit Format of the Clock Select Registers, CSRA and CSRB Field CSR[7:4] CSR[3:0] X=0 6 1<6 1 / 6 < <= > / 1=<: ( 2! /5 2! 5 ACR[7] = 0 X=1 >6 1<6 6 1/ <<: ==: 6>/: 6: <= = / : ( 2! /5 2! 5 X=0 >6 1<6 6 1 / < <= = / : ( 2! /5 2! 5 Bit Rate ACR[7] = 1 X=1 6 1<6 1/ <<: ==: 6>/: 6: <= > / 1=<: ( 2! /5 2! 5 Note: the b suffix denotes a binary expression. x = don't care value. Table 18. Bit Format of the Clock Select Registers, CSR[3:0] and CSR[7:4] Please note that = calls for the user to specify the following parameters4 N>O % %(- (+(' ( * + !( (& -(% 5 2! $ ( N>O (% * + !((& -(%" $ ' %(& -$ & (( - !!!!!!! !!!!!!! " ( $ % '" %'(& 66 X - The Select Extend bit 2' %( $ '(" (( % ! $ ( ' % '$ & (( - ( $ ' H% $ -(% - (% ( +( ' + $ ( Table 3 Table 19 %(I% % ' $%" $ ( ++' 2! $ (% XR88C681 Register $ -(% " $ -(% " $ -(% *" * $ -(% *" * Contents =/ / / */ Resulting Action ! *0 ' 2! $ *( 5 J ! *0 ' 2! $ *( 5 J ! *0 ' 2! $ *( 5 J ! *0 ' 2! $ *( 5 J Table 19. Command Register Controls Over the Extend Bit Note: If the user programs either nibble of the Clock Select Register (CSRn[7:4] or CSRn[3:0]) with values ranging from 016 to C16, then the user is using the BRG as a source for timing. However, these standard bit rates (presented in Table 18) apply only if the X1/CLK pin is driven with a 3.6864 MHz signal. If a signal with a different frequency (fo) is applied to the X1/CLK pin, then the DUART channel is running at the following baud rate: Actual Baud Rate = N / *$ ;O R + 1/=/< 8I provided that fo is between 2.0 MHz and 4.0 MHz. Additionally, as in the case for standard baud rates, the actual frequency of the clock signal will be 16 times these values. 1X vs 16X Clock Signals % C5 '3D $ C/5 '3D ($ - (% ! +" ( (% ( $(%'%% ( ( - $ %(- (+(' ' C/5 ''3D %% '($ %( $ & +' + / B% C5 ''3D & %% %(- % ' ( ($ (% %$ ''& ' '$ - '''& ( % '($ ( % + /5 ''3 ( ( + 5 ''3 +( - -% ( '(+& % % '( ( + ' % (% ''3$ & ' (( - %' + (( - *'3 #+ (% '( (% '( $ (% '(( - $ + %( %(" %( (% % ''3$ & (% ' (( - %' 8 '" (% - ''3 +E '& + '( (% !'& % % + %( (% (% ''(%(' + %& ' % %( $ ' ('( - '( $ %( -$ '( $ %( $ !'& % $ " %++('( $(++ '% ( +E '(% + ''3 %'% ' '( $ %( ' ' ( ( % ( '(( - '%%" % % $ ( +( - $(%'%%( 6/ % %( $ %(%%( %&% % $('$ ( Figure 29 (% %&% ' %(%% + %( 5" $ ' '( 5 %( 5 '( 5 5 '3 5 '3 Figure 29. Example of a Serial Data Transmission System 9 % + %% '( (% ''3$ & %' (% %(-& +% + %(" $ '( (% & %( - %( $ ' ( ($ Figure 30 % % %% + (% XR88C681 Figure 30. Receiver (1X) Sampling, if the RX Clock is Slightly Faster Than the TX Clock Figure 30 %% % ( %( '(H% %( - ( $ ' %( $ ( (% ' -( - # (% '%" '( (% %( - ' %( $ (" ( $ ( ( ( ($" ( ' %''%%( $ ( (% (% 3 % '( $(+ #+ (% ''( + '( $(+" ( & % ( %(%%( $ '( + (% %( $" % $('$ ( Figure 31 '($ ' Figure 31. Illustration of an Error due to Receiver Drift Figure 31 %% '( %( - (- ( %( - + $ ( ( It is interesting to note that, in Figure 31, the Receiver sampled 01010010 # %$ $ '( $(+ ' % (% ' '( (% % %( ''3 6> XR88C681 # - (" + (% C ''$D %&% (% + '( + (( - $(++ '% 5 $ 5 ' ''3 %(- % 8" ( $ '' + '( (+ $ ( ((I *2 $( - %( $ %(%%( " & % ( 3 '" & '( %( - + ( B (% + (% &$" '(" $'( + (" ( -( %( - (% ( & % ( - +' &('&" + % % $& %" (% % +' (% / 5==/= $(' % ''$% /5 '( %( - + ( +" ( % $('%" '( $'% '' ' + (" ( '( ( -( %( - (% ( & +' + / 8" + > /5 ''3 ($% % %$" '( ( %% (% ( (( ( ($ ( + ( ($" $ ( '% %( - + ( $ + %%E $ (% ( " - $ + ''" '( ( % %( $ % 5 $ &" ' '( % '$" ( (% ($( + (" '( (" + ( " -( %( - %( $ ( ($ ( % Figure 32 + '( % '($ , (" ( ( ( '' ' + ( ' ( % $'$" (% %( - '$ (% $ % % ($( + *( *( ,($ > /5 ''3 ($% Figure 32. The Typical Sampling Pattern of Each Receiver Within the XR88C681 Device. 6= XR88C681 %( - ' (E ((-% & + %( $ ( % & ( - $M% '( %( - ( " ($( + ( ($%" '' '' %(% (% ' (% %''%%+ + % %4 # ++% ($(' ''( '( %( ( # ((% '( $(+ %( - ( $M% % &('& % (% = ( '' A (& $ , (% +" (+ % %'% '( $ $ + / $L $'( + (" '( ( -( %( - $ / ! / J 61"/8I 8" ' '( % %$ > 61/38I ''3 %" ( ( 3 (% '( % ($( + ( (% ( " 61/38I ''3 %(- (% $(($$ & / - % ''3 /8I + ( ( $ $ $ (% + '' 5==/= $('% -(% % ( $' ! ( ''3 %(- % ( 5 /5 ''3 %(- B % (% -( '(' % ( 5 /5 ''3 %(- '3 ' -(%%" % (% $(%$ &% % /5 ''3" ( $ ((- ++'% + '( $(+ % (% + $(%$ % 5 ''3 +% + " %% ( '( - %( $ % (% %& ' % ( '( 5 ''3 D.6 Application Examples using the Timing Control Block # $ '(+& % + %%% (( (( *'3" !% ( '$$ Example A: Using the BRG % % (%% '( $ %( $ + 63% ( % % $ +( -4 % 1/=/< 8I '&% %'( '%% 5.9: $ 5 ( %L $(( - 1/=/< 8I 9 %(- ( 5.9: ( ( 5 ( +( - B( / $ -(% (% % ( % %( *0 ' 2! $ ( 5 J 1 B( =/ $ -(% (% % ( % '( *0 ' 2! $ ( 5 J 6 < B( !!!!!!! (% % %'% C*( D S Table 18 + (% $ % B %++(! $ % ( & !%%( " $ ! $ % C$ H 'D + ( & !%%( 6 B( ==/ (% % %% '( $ %( ( + 63% Table 17 $ Table 18 Example B: Programming the Bit Rate via the Counter/Timer % % (%% %( $ '( $ /63% ( * Please note that this particular bit rate is not offered by the BRG # (% '% % ' $ +( - ( < 8I 9 %(- ( 5.9: ( " ( 5 ( (% + +( - B( / $ / 9 (% %% %% ( . - ( - %E + +E '& J < 8I.NO J 8I 1 B( N/4 $ %' (( - %' + . 5.9: ( < B( / * (% ( %'(+& (( %' + '( $ %( + * ( $($ + . Please note that when the DUART is programmed in this configuration, the C/T output represents a 16X over sample of the Transmitted and Received data +" '( '('(& ( $(($ 8I %E & /" M% (3 + ''3 %(- % (-( ( - + *0 %4 *( J 8I./ J /63% Example C: Using the External Input Ports % " ( $$(( ( - * /63% % 2! *" .% % %( $ '( $ % ( % $% + + %% % $ ( 2! *" - ( +( -4 B( !!!!!! , +(-( -(% , (% % % 8I %E + . ,1 74 ! J $ H ' %++(! $ % ( & !%%( XR88C681 2! & ' ' ,1 ( #,1 $ #,< ( % & &( - 8I %E ( % ( ( % 1 B( / incoming serial data stream is synchronous with the 1 MHz (1X) clock signal; in order to minimize bit errors (% % ( %'(+& (( - %' + %( $ '( + ( $($ + ( ( % #,1 $ #,<" %'(& $$(( &" (% % $ % % ( %(- 5 %(- % 8 '" (% $((%( &/ + (% %(- +" ( + (% % Please note that if the user were to apply this example, he/she would be responsible for ensuring that the Symbol 9: +9: + 5 +5 +5 /5 +5 5 Parameter 5.9: 2! 8(- 9 ( 5.9: &% 2! E '& .( 2! '3 8(- 9 ( #, # D.7 Explanation of Clock Timing Signals % + (% %'( (% !( %'(+('( (( - *'3 % # %" (% %M' % %' + ' %($ ' +%( & % %% 5==/= % % +( %'(+('( % ( C 292# 9 8 2##D Min. < 1/=/< < Typ. Max. Units % 8I % 8I % .( 2! '3 E '& #, # 5 $ 5 2! 8(- 9 ( ( #," #,1" #,< $ #,6 5 $ 5 2! E '& ( #," #,1" #,<" $ #,6 /5 5 8I 8I Table 20. Clock Timing (Figure 13) 7" (% ! ( + ' + % % tCLK - X1/CLK (External) High or Low Time &% $& (' -(' - ' + (% '('(& +" ((% 9: $ +9: $$ ( $ % $(' ( + '( & (% M% '% (( + ( %(- ($ - 5.9: ( % %($ (- $ %% fCLK - X1/CLK Crystal High or Low Time (% %'(+(% - + +E '(% (%%( 5.9: ( " ( ( '&% %'( ($ 9 ( %(- +" % ' & & $ < 8I (% ( tCTC - Counter/Timer External Clock High or Low Time - IP2 Input (% '% (( + ( %(- " ( - ($ #, ( " + % & .(" ' %($ (- $ %% Please note that this limit has no relationship with the parameter tRTX, which is another spec associated with the IP2 input. fCTC - Counter/Timer External Clock Frequency IP2 Input (% '% (( + ( +E '& ( - ($ #, ( " + % & .( %' %('& %% %(- ( +E '& < 8I ' ($ #, ( " $ %( & $$ & .( (% %' (% $ 5" (' % / XR88C681 %'(+(% ((% %(- % ($ #, ( ( %" + % 2! '3 ' + %( $ '(% tRTX - RXC and TXC (External) High or Low Time - via IP2, IP3, IP4 and IP5 (% %' '% (( + ( %(- " ( - ($ 0 ,% # ,( %" #, #,6" + % % %( $ '( '3 %'" ' %($ (- % (% %' % ( %( " - ( (% % (% # ( #, fRTX - RXC and TXC (External) Frequency - via IP2, IP3, IP4, and IP5 (% %' '% ((% 5 $ /5 ! %(- % %$ ''3 %(% $ '(% #+ % (%% % 5 ''3" .% ' & & %(- ( +E '(% 8I (% ( ( %% ( ( + % % 2! #+ % (%% % /5 ''3" .% ' & & %(- ( +E '(% 8I ( ' (% %(- (% /5 %(- " (% ( % ( ( + 63% # %&" (( - '3 -(% % ((& - (& & $ % $%(% (( - *'3 -(% % ''%% +( - %'%4 1 $(++ % $$ ( % ( *0 .(" (' ' ' +(-$ - ( % (' ( + *0 # % (( - *'3 ( % # , ( % (' % % + ! ''3 %(- % - '% ( E. INPUT PORT # , ' %$ % - % ( ' -$ % % + % ( % + %'( + '( % ' % + ( % (% '$ ' $ & , & $( - #, -(% + %% + #, #,6 (- ( %(- #, ( %% ( -(' CD ( #,N O ( %(( " (( #, -(% 9(3(%" CD ( %(- #, ( %% ( -(' CD ( #,N O ( %(( " (( #, -(% E.1 Alternate Functions for the Input Port Table 17 $%'(% %% + ( ( %" %' % ''3 ( % $ $ + ' %(- % $ ( '$% (+ %& % - + '( $ + #, -(%% ( % -(' % ( " -$%% + (% -$ + '( / XR88C681 Input Port #, Alternate Function(s) Approach to Program Alternate Functions #, ' -$ + '( % ( & %( - N (% + '( " % % Section G.3. CTSA4 $ ( + 74 (% ( (% '( 9" + + '( #, CTSB4 $ ( + * #, ' -$ + '( % * 74 (% ( (% '( 9 + + '( ( & %( - *N (% + '( " % % Section G.3. #, ' -$ + '( % ! ''3 ( + .( & %( N/4 ++' + (% '( % % Section D.2 #, ' % -$ + '( % ! ''3 ( + '( + * & %( - *N>4 '( % ! ''3 ( + %( + & % ( - N14O J N" " " O + /5 '3" N14O J N" " " O + 5 '3 #,< ' -$ + '( % ! ''3 ( + '( + & %( N>4 '( % ! ''3 ( + %( + * & % ( - *N14O J N" " " O + /5 '3" *N14O J N" " " O + 5 '3 #, CT_EX4 .( 2! '3 # RXCB4 2! '3 ( + '( * #,1 TXCA: 2! '3 ( + %( #,< RXCA4 2! '3 ( + '( #,6 TXCB4 2! '3 ( + %( * Table 21. Listing of Alternate Function for the Input Port E.2 Input Port Configuration Registers (IPCR) - + % $'% ($$ + ( ( % #, - #,1 % ( % %$ & 1=<38I + *0 <3% ! / (- (- %(( % ( %( - % ''3 ($% !(& 6* % ( - '% $( - ( ( ( ' - -(% #, ( %" - ( & % & ' - + % % % % 6* % ( + + #, +% %% (% ( #, #,N>4 & ' - + % ' % -$ - ( ( C# , - + D ( Bit 7 Delta IP3 J 7 J G% Bit 6 Delta IP2 J 7 J G% Bit 5 Delta IP1 J 7 J G% Bit 4 Delta IP0 J 7 J G% Bit 3 IP3 J 9 J 8(- Bit 2 IP2 J 9 J 8(- Bit 1 IP1 J 9 J 8(- Bit 0 IP0 J 9 J 8(- Table 22. Input Port Configuration Register - IPCR / XR88C681 # $ C# , - + D ( " % $ +( - B( ( $ ( + ( +% + (% % $ ( Table 23 Please note that the applicable bits, within the ACR register, are shaded. Bit 7 BRG Set Select J J Bit 6 Bit 5 Bit 4 Bit 3 Delta IP3 Interrupt J J 7 Bit 2 Delta IP2 Interrupt J J 7 Bit 1 Delta IP1 Interrupt J J 7 Bit 0 Delta IP0 Interrupt J J 7 Counter/Timer Mode and Source Table 7 Table 23. ACR- Auxiliary Control Register ( - #N>O Note: This "two-tiered" interrupt enabling/disabling approach, for the "Input Change of State" interrupt allows tremendous flexibility for the user. Setting or clearing the bits in ACR[3:0] allows the user to specify exactly which Input Port pins to be enabled (or disabled) for generating the "Input Port Change of State" interrupt. Setting or clearing IMR[7] allows the user to "globally" enable or disable this interrupt. ( + #, ( ( $(' (' + + ( ( % !( '$ C - + D ( + #, ' ( % % % + % ( ( % +" $( - #," ( % % C - + D ( " , ( $( 4 ( ( % --$ +( % + ' -( - ( ( E.3 28 Pin Packaged DUARTs = ( '3-$ % ' ( & ( ( " #, +" & ( + '( % ( $(' ( (% ( ( .25 . 2! '3 # $ 5* 2! '3 ( + '( * F. OUTPUT PORT ' %(%% + = ( , , ' %$ % - % ' %$ + (( - $ %% %(- % & (& -( - + $ -(%% " * $ " * $ % ' +(-( -(%" , B %$ %% %(- % , ( % $( " (' % ( % ( ( ( %' ,-( - , (% ( $(++ + ' ( (% &(' $ % , '('(& ' %(%% + , /1 -(% ," $ ( % %% ' % + , ' % + ' % + , ( % 2!4 #+ ( ,N6O (% % -(' CD" (% ( % ( ,6 ( ( - -(' CD 9(3(%" (+ ( ,N6O (% % -(' CD" (% %% ( ,6 ( ( - -(' CD ( - 3% -( - ( $$ (% '$ % % ''(% (% + B (( - (% " % ( 3 + $$%% (--$ ' $%4 2 , , *# $ 92 , , *# It is important to note that when invoking the "SET OUTPUT PORT BITS" command, the user is setting the bits (to logic "1") in the OPR 8" (% '( %% ( %( - '% $( - , ( % -(' CDL $ ' & ( %( % + , ( % $ (% ( , 9(3(%" 92 , , *# ' $ (% ( 3$" %'(+($ (%" (( , C'$D -(' CD 8" '% $( - , ( % % -(' CD % % + ' ( (( ," +( - , % ," (% CD +" % + ' , ( " +( - , (% -(' CD (% + , ' % $ '$ ( $(($& ( (% % & $$%%(--$ C2 , , *#D ' $ % Table 1 ( '' &( - XR88C681 $" *%" %'(+&( - (%" (( ," % J %" J ' - ( (% '$ & $$%% (--$ C92 , , *#D ' $ % Table 1 ( '' &( - $" *%" %'(+&( - (% % J '$" J ' - F.1 Writing Data to the OPR/Output Port Pins % ( $ (" % + , $ ' %E &" , ( % (% ' $ & C $$%% (--$D ' $% , *(% $ , *(% $ '$ $ ++' + %( - % ' $% $(%'%%$ ( Section F.1.1 F.1.1 Set Ouput Port Bits Command ' '$ %$ ( 3 C2 , , *#D ' $ (% % % (( - ' % *% > $$%% 2/ + ,> , & CD !(%% (( '$ ' % + *%" '% $( - (" (( , (% % -(' C(-D & CD (% % $ % $ (% ( $$%% 2/" % + '% $( - (" (( , (% ' -$ B '$ % (% & %4 & CD (% % *%" $( - % + C2 , , *#D ' $" '% $( , ( (% % -(' CD $ + & CD (% % *%" $( - (% ' $" % + '% $( - , ( (% ' -$ 2!4 % ' + , ,N>4O J N" " " " " " " O 8 '" % + , ( % % +%4 N,>" ,/" ,6" ,<" ,1" ," ," ,O J N" " " " " " " O #+ ( +( - $$%% 2/L N>""O J N" " " " " " " OL %( - % + , -(% *(% +%4 ,N>4O J N" " " " " " " O %E &" % + , ( % % +%4 N,>" ,/" ,6" ,<" ,1" ," ," ,O J N" " " " " " " O (% ! + C2 , , *#D ' $ (% (%$ ( Figure 33 + , ,( % ,> , # (( ,N>4O *%" > $$%% 2 ( ,N>4O Figure 33. Illustration of the "SET OUTPUT PORT BIT" Command and its Effect on the Output Port Register and the State of the Output Port Pins. /< XR88C681 # %&" + C2 , , *#D ' $L J L %% ( ' - + ,N O" , ( , J L %% ( ,N O J CD" $ , ( " , J CD % + '% $( - , -(% (" $ ( % + , ( (% ' -$ 2!4 % ' % + , -(%" , J N" " " " " " " O %E &" % + , ( % 4 N,>" ,/" ,6" ,<" ,1" ," ," ,O J N" " " " " " " O #+ ( N>""O J N" " " " " " " O $$%% /" %( - ' % + , -(% ( 4 ,N>4O J N" " " " " " " O " %( - % + , ( % ( 4 N,>" ,/" ,6" ,<" ,1" ," ," ,O J N" " " " " " " O (% ! + C2 , , *#D ' $ (% (%$ ( Figure 34 + , ,( % ,>, # (( , N>4O F.1.2 Clear Output Port Bits Command '$ + ( 3( - (% ' $ (% & %(( + C2 , , *# 7DL !' ( % (% $$%% / + N,>"",O & CD (% C( D (% $$%%" '% $( - ( ( , -(% (% % -(' CD $ '% $( - , ( " , (% % -(' C(-D & CD (% ( (% $$%%" *%" > $$%% ( , N>4O Figure 34. Illustration of the "CLEAR OUTPUT PORT BIT" Command and its Effect on the Output Port Register and the State of the Output Port Pins. # %&" + C92 , , *#D ' $L J " %% ( ' - + ,N O $ ' - ( % + , ( " , /6 J " %% ( ,N O J " $ %% '% $( , ( -(' CD XR88C681 F.2 Output Port Configuration Register (OPCR) , ( % ' %$ % 0 ,% ( %" & ' ' +(-$ %$ ( + '( % Table 24 (%% '( % + ' + , ( % Output Port , , , Alternate Function(s) RTSA4 E% $ + 74 (% (% '( 9 + + '( 9 + + '( RTSB4 E% $ + * 74 (% (% '( TXCA_16X Output4 /5 %( '3 TXCA_1X Output4 5 %( '3 RXCA_1X Outpu4 5 '( '3 TXCB_1X Output4 * 5 %( '3 RXCB_1X Output4 * 5 '( '3 C/T_RDY4 .( $& + . S 74 (% (% ( %$ % .( $& RXRDY/FFULL_A Output4 '( $&. # # $(' 74 (% (% ( + 5G. 99. + '( RXRDY/FFULL_B Output4 * '( $&. # # $(' 74 (% (% ( + 5G. 99.* + '( TXRDY_A Output4 %( $& # $(' (% (% ( + 5G. + '( TXRDY_B Output4 * %( $& # $(' (% (% ( + 5G.* + '( ,1 ,< ,6 ,/ ,> Table 24. Listing of the Alternate Functions for the Output Port & + '( % + (% , ( % %'$ & (( - ( $ , ( + + (% -(% +% Bit 7 OP7 J ,N>O J 5G* Bit 6 OP6 J ,N/O J 5G Bit 5 OP5 J ,N6O J 5G. 99* Bit 4 OP4 J ,N Table 25. Output Port Configuration Register - OPCR // XR88C681 F.3 28 Pin DIP Packaged DUARTs = ( #, '3-$ $('% & %" , $ , 8 ' ++' + C2 , , *#D $ C92 , , *#D ' $% & ++'% % ( % $$(( & $ * & ( ( + '( % ( (% %( + 5==/= (% %'( + $ % $(%'%%% %'% ( ' ' % %'% (%$ 4 %( %( 8$( - -(% $ %( (+ -(% '( '( 8$( - -(% $ '( (+ -(% % -(% $ -(%% $ -(% Section B.2" $ '$( - '3 ' -(% Section D" (( *'3 G.1 Transmitter (TSR and THR) %( ''% $ + , $ ' % ( %( ( % ( (% 5 ( " $$( - %" % $ ( (& (% % E($ & %& ' % ' 2' %( ' %(%% + %( (+ -(% $ %( 8$( - -(% 8 8 (% '& & # Figure 35 % % %((+($ (%( + $ 8 , ( ((% %(%%( + %( $ & (( - '' $ 8 '' ( $$ ( $ '%%$ - # " ( ( '% ( - %(( + 8 " '' $ (% %((I$ $ (% %($ + '( ( 5 ( G. SERIAL CHANNELS A and B 2' %( ' + '(%% +$! %& ' % '( $ %( ' % ' ( $ $ & %' ( ( +E '& + *0" ." ! ''3 % % ( - $ *%($% $ ( (' '( $ %( + ' ' ( $ $ &" ' ' +(-$ ( (% ( - $%" (' %+ + ' $ $(- %('%" % % ( 3 $ %$ + ($ ('( % # (% %'( '( %&% ( %$ $ '( %'% + %( $ '( $+( (( + % + % %&% +% 5 %( ( + 5 %( '3 (- + 5 '( ( # + 5 '( '3 (- + 5 %( '3 + (( - *'3 %( (+ -(% 5 -( ( *% , + , %( 8$( -(% Figure 35. A Simplified Drawing Depicting the Transmit Shift Register and the Transmit Holding Register. /> XR88C681 B %( (% ($ ( '(" 5 + (' ' ( ' ( %& 3( - -(' C(-D 8" M% ( %(%%( + ''" %( % '( & - ( - C D ( ( (% %('& 5 --( - CD + ( ($" +( - ($ ($ , ( + '$( '' #$(& + %(%%( + (" % %(- (+(' ( + '' ( % +(%" +$ & -%%(& %(- (+(' (% #+ ' ('( ' '% + (" %( ( % $ C(&D ( % %(- (+(' ( + '' $ , ( Figure 36 % % + + + %( 5 # (% '%" %( (% % $ 6/" ( =7 ' = (% ''" 7(&" *( %( #$ *( 5 *( *( Figure 36. The Output Waveform of the Transmitter While Sending 5D16 (8-N-1 Protocol). ' -$ - # E% , & %( - #NO $ #N $ *" %'(& # (% '%" $ - # E% &( %( 8 $ & + ''% , ' %(' (% ( E% & (( - '' & 8 %( ' $ $(%$ ( $ -(% % Section B.2 #+ ' $ (% (%%$ $(% %(" ( %( ''% ( 8 $ " %( ( ' ( %(( - + ( ( - $ (( 8 $ " ( & '& & + ''% 7 ''% ' ( 8 ' # *92 7#2 ' $ % (%%$ /= G.2 Receiver (RSR and RHR + '( + %( '( (% '( %( $ 5 ( L ' ( $" ( ' $ & , '( (% % % %( + '( - $ ''3( - (&" (+ (& (% ( - %$ '( ' %(%% + '( (+ -(% $ '( 8$( - -(% 8 8 (%" ( %% '" & # '( '(% $ 5 ( " ( (% '%%$ - +$%" $ (% ' $ +" $ (% %+$ 8 (% '' (% '%%$ - 1 &% + # ' '($ '' '% + # " ( ' C$D $ & , L ( $% 8 Figure 37 $('% %((+($ $( - + '( XR88C681 # '( ( 5 '( (+ -(% '( '3 + (( - *'3 5 *% $ & , '( 8$( -(% Figure 37. A Simplified Drawing of the Receiver Shift Register and Receiver Holding Register '( + '( % & % %( - - 5 ( B + $ %( (% ($" (% 5 $ ' %E &" 5 ( (% ' ( %& C3( -D ( - (% ($ '( (% ( '( $ (% '(( - '%%( - & $ 8" + $ %( % $% (" ( (% 5 --( - CD" '( ''3" (' (% / (% $ ( /! ''3" ( % %( - (% ( #+ '( $( % (% 5 ( (% %( CD + (% > %" '( $ ' %($% (% %(- ($ ( #+ 5 ( (% CD > %" '( ( (- (% $ $ % % C (%D (% > % " '( ( % ' %''%%( ( (($ ( % .$ ( ! ''3 % + (% /! '3 (% +$ (+& $'$ CD ( 5 ( (% ( $$ ( / %(% % ( %( ! ( %( - ''3" $ ( '( - %( $ % ($ (% % ' $ ( ( ($$ + (% ( ($ Please note that if a 16X clock is selected for the receiver, this over-sampling procedure occurs with each and every start bit. '( ( ' ( % $ '( ' ( + '' +% (" ( ( ( % '( + ''H% * '( ( ''3 (& (+ -$ ( % + , ( #+ '( %% 3 ' $(( (% ( $ (& ''3 (+ & % ($L %''%%+ '( + '' (% %$L $ '( ( % % $ % '' ' + ( + ! '' XR88C681 Receiver Errors #+ '( $% % C3D" %$ ( + , (" ( - 2 2 (% +--$ & %( -" N/O J #+" ' '( + ''" %%E (& ''3 (% ( ''" ,(& 2 ,2 (% +--$ & %( - N6O J #+ 8 % +" $ '' !(%$ ( L $ (+ $ % ( '% $( 5 ( L '' ( ( ( " $ '( 2 2 ' $(( ( +--$ ( % -(% N %% + $ ( & (+ 5 ( (% $ %' ' $(( + ( '' ($" $ , ( % $'$ , ( %( - %$ ( %'L '($ *3 * ' $(( (% %$ B (% ' $(( (% $'$ % ( -% C'($ *3D ' $(( (% +--$ ( % -(% N>O J C*3D '' (% $$ ( 8 8" + $ (% '($ $$ ( 8 ( 5 ( % C3D ' $(( 1 '% $( - C *3D ( (% E%$ (+ -$ $ +--$ ( # % -(% ' 5 ( % C3D ' $(( " %%E ''% ( $$ ( 8" $ '% $( - C *3D ( ' $(( ( ' -( E%$ (+ -$ $ +--$ ( # % -(% ' -$ - # E% , (+ 5G '( $& 99 # $(( !(%% + ( ' 5G $(( !(%% % '' + $ !(%% (( 8" $ (% (& (( - C$D $ $ & , 99 ' $(( !(%% 8 (% '& + $ ' '' & ''% + ( , % $ C$D # % ' %' # E% '' $ ( 5G 99 ' $(( ( $ -(%% % ( % $ & %( - #NO $ #N6O + % $ *" %'(& 2' ' (% E($ ( % -(%% %$ ($ ' $ (( - + % ' % + % -(%% $(%'%%$ ( ( %'( % + $ % 8" $($ $(%'%%( + ( $ + % -(%% % $ ( Section G.3 G.3 Mode Registers, MR1n and MR2n $ -(%%" % %'(+& + ' % .% (% ' % -(%% % % ' +(- ' % -- ( $ $%3( ' (E% (% + ' + % -(%% $(%'%%$ ( Table 26 Bit 7 Rx RTS Control J 7 J G% Bit 6 Rx Interrupt Select J!G J 99 Bit 5 Error Mode J' J *'3 Bit 4 Bit 3 Bit 2 Select Parity J 2 J $$ Bit 1 Bit 0 Parity Mode Select J B( ,(& J ' ,(& J 7 ,(& J ( $ Select Number of Bits per Character J 6 J / J > J = Note: MR1n for each channel is accessed when the channel's MR pointer points to MR1. The pointer is set to MR1n by a hardware RESET or by a "RESET MR POINTER" command invoked via the channel's command register. After any read or write to MR1, the MR pointer will automatically point to MR2. Table 26. Mode Registers - MR1A, MR1B > XR88C681 Bit 7 Bit 6 Bit 5 Tx RTS Control J 7 J G% Bit 4 CTS Enable Tx J 7 J G% J 6/1 J /6 J /== 1 J >6 < J =1 6 J =>6 / J 1= > J Bit 3 Bit 2 Bit 1 Bit 0 Channel Mode J 7 J 2' J 9' 9 J 9 Bit Length = J 6/1 J /6 J /== * J >6 J =1 J =>6 2 J 1= J Table 27. Mode Registers - MR2A, MR2B MR1n[7] - Receiver Request to Send Control $( (&" E% $ (% %%$ -$ & ( 3( - C2 , , *# 7D C92 , , *# 7D ( ( 8" (+ N>O J (% %" '( ( ' -( + '(+('&" %( - (% ( ( '( - (+ (% 8 (% + (% C+ ' D ' (E (% %+ ( ( - '( 2% Figure 42 % % $(- (' (%% '( $ E% $ ' +(-( $ + '( MR1n[6] - Receiver Interrupt Select (% ( %'% ( 5G %% ( 99 %% ( + ' %$ % '(( + - ( - # E% , " #NO + $ #N6O + * MR1n[5] - Error Mode Select (% ( ' % ( + # %% (% ,2" 2" '($ *3 + #+ (% ( (% % CD" (% (' ' ( ( C'D 2 $ #+ (% (% (% % CD" (% (' ' ( ( C*'3D 2 $ # '' $ % %% (% & & '' (% ' & + # # '3 $" % (% % '( -(' > + %% + ''% '( - + # %( ' % C22 2 D ' $ + % (%%$ MR1n[4:3] - Parity Mode Select #+ C( (&D C+' (&D ( (% -$" (& ( (% $$$ %($ ''% $ '( +% (& ''3 '($ ''% Section H.2 + $%'(( + ( $ ( MR1n[2] - Parity Type Select (% ( %'% 2;27 (& (+ CB#8 , #G 2D (% -$ $ % + +'$ (& ( (+ C 2 , #GD $ (% -$ # ( $ ( %'% % + . +- ( (% ( % ++' (+ C7 , #GD (% %'$ ( N<41O MR1n[1:0] - Bits per Character Select '% + (% %($ $ '($ ( $ +($ + '' (% $% ( '$ " , #G" $ , (% Mode Register 2 (Channels A and B) + ' (% ''%%$ H% ,( ( % " (' ''% + & ''%% H% -(% %E C$%D C(%D $% ' - ' % + ( XR88C681 MR2n[7:6] - Channel Mode Select 2' ' ( + + $% ( - N>4/O J ' +(-% ' ( 7 $ # (% $" '( $ %( ( $ $ & Figure 38 % % $(- $('( - 7 $ ( ( - N>4/O J '% ' ( (' 2' $" (' ('& %(% '($ $ Figure 39 % % $(- $ ('( - (' 2' $ ( + ( - ' $(( % & ( ( (% $ 5 5 # '( ( 5 5 -( - ( '( (+ -(% %( (+ -(% %( 8$( -(% '( 8$( -(% = = *% $ & , *% , $ + , Figure 38. A Block Diagram Depicting Normal Mode Operation. > XR88C681 5 5 5 # '( ( '( (+ -(% %( (+ -(% 5 -( - ( %( 8$( -(% '( 8$( -(% = *% $ & , , % ''%% %( Figure 39. A Block Diagram Depict Automatic Echo Mode # (% $4 '($ $ (% %($ ' H% 5 '( % $ %( $ $ 1 ' H% 5G $ 52 %% (% ( '( < '($ (& (% ''3$ (% - $ + %(%%( %" %($ (& (% % '($ 6 ' +( - (% ''3$ % (% %($ % '($ >1 / '($ 3 (% '$ % '($ ( ! ($ % ( (% $'$ > , '( ' ('( % % &" , %( ( 3 (% $(%$ 2' ' ' ' +(-$ ( + $(- %(' $% Local Loopback Mode (% $ (% %'$ & %( - N>4/O J Figure 40 (% $(- $('( - 9' 9'3 $ ( XR88C681 ; 5 5 '( (+ -(% %( (+ -(% 5 %( 8$( -(% '( 8$( -(% = = *% $ & , *% , + , Figure 40. A Block Diagram depicting Local Loopback Mode Operation # (% $4 %( (% ( & ' '$ '( ( %( ''3 (% %$ + '( 1 ' H% 5 (% $ 3( - (- < ' H% 5 ( (% (- $ 6 %( (% $" '($ $ $ / , %( $ '( ' ('( % ' ( & >< Remote Loopback Mode. (% $ (% %'$ & %( - N>4/O J Figure 41 % % $(- $('( - 9'3 $ ( XR88C681 5 5 # '( ( 5 5 '( (+ -(% %( (+ -(% -( ( %( 8$( -(% '( 8$( -(% Note: The CPU has no access to the Serial Data during Remote Loopback Mode. Figure 41. A Block Diagram Depicting Remote Loopback Mode # (% $4 '($ $ (% %($ ' H% 5 '($ $ (% % , $ %% ' $(( % ''3$ 1 ,(& $ +( - % (% %($ % '($ < '( % $ 6 '($ 3 (% '$ % '($ ( ! ($ % ( (% $'$ MR2n[5] - Transmitter Request-to-Send Control $( (&" E% $ (% %%$ -$ & ( 3( - C2 , , *# 7D C92 , , *# 7D ( ( " & %&% %+ 8" %( - N6O J % %( - ('&" ( >6 ( + ''% ( $ 8 %($ $ & Figure 44 % % $(- (% %( $ E% $ ' +(-( $ + '( MR2n[4] - Clear to Send Control #+ (% ( (% " ' % ( #, + " #, + * % ++' %( #+ ( (% CD" %( ( ''3 % + (% ( ' ( (% ( $& % $ '' #+ (% CD" '' (% %($ #+ (% (- -$" 5 ( % ( 3( % $ %(%%( + ! '' (% $&$ ( -% -% ( ( ( '' (% ( - %((I$ $ ++' %(%%( + '' (% (% + (%$ ( Figure 42 $ Figure 44 XR88C681 MR2n[3:0] - Stop Bit Length (% ( +($ -% $( + % (% $$ ' %($ '' ( $( + ./ ( ( $ ./ ( (%" ( ( ' % + ./ (% ' -$ + '' -% + /" > $ = (% 6 ( ''" % ( $( ' -$ + ./ ( (% #+ ! ! ''3 (% -$ + %( ''3 5 " N1O J %'% % ( $( + ( ( $ N1O J %'% $( + ( (% + %(%%( '( & ''3% + 3 ' $(( ' + +(% % ( (%" ( ( + % $ (& ( (% %$ -$%% + -$ %($ % ( - #+ '( $% % C3D C 2D 2 (% +--$ ( % -(% Bit 7 Received Break J 7 J G% Bit 6 Framing Error J 7 J G% Bit 5 Parity Error J 7 J G% Bit 4 Overrun Error J 7 J G% G.4 Status Register, SRn % -(% ($% % ( %% 8 $ 8 '( $ %( # %" %'(&L $ %% ($ , ( % + E(& + '( + $ & '( # % ( $('% %+ ( $ %&%% $ % , ''3 $ % (+ %( (% & $. (% $& + $ + , # % ( $('% % ( $(' 8 % ''" (' (% (( - $ & , " (% + $ ( ' + '(( - & ''% ( %( $ '( # %% ( $('% '$ ( ( + % -(% ( + % -(% % % + & $ '( % (+ + % -(% $ $(%'%%( + ' ( +%4 Bit 3 TXEMT J 7 J G% Bit 2 TXRDY J 7 J G% Bit 1 FFULL J 7 J G% Bit 0 RXRDY J 7 J G% Table 28. Status Register - SRA, SRB SRn[7] Received Break (% ( ( $('% I '' + -$ '' - % '($ ( % ( & %( - # %(( (% ''($ 3 (% '($ $$(( %+% ( # ( (($ ( 5 ( % 3( - % + % + ( ( (% (% $+( $ % %''%%( $-% + ( ! ! ''3 B (% ( (% %" ' H% C8 702 #7 *2 : D ( ( # (% % ( ( # (% % % $ + 3 ' $(( " % $+( $ " (% $'$ '(H% 3 $' -(' ' $' 3% -( ( ($$ + '' 8" 3 % %(% ( $ + ! '' ( ( $ + ( $'$ #+ 2 $" + ' " % % C'D $" (% ( & (% ' + 8 (% ( ( '$ (+ 5 >/ ( (% - -(' C(-D " ( ! '' #+ C2D $ % % C*'3D $" (% (" ' % ( ( %%$ ( C22 2 D ' $ % ( 3$ % % Table 3 Please note that if the Error Mode is "Block" this bit, in the Status Register will remain set, for all subsequent characters, independent of the condition of these received characters, until the "RESET ERROR STATUS" command has been invoked. SRn[6] Framing Error ( - '( + '' (%" $ & %%'($ (& (" '( ( ''3 + C3D ' $(( (( +( - % $ (& ( (% C3D ' $(( (% , ( #+ '( $% $' C3D (% (" ( (% --$ C(-D +--( - '' ' + 2 2 #+ 2 $ % % C'D $" (% ( & (% ' + 8 #+ XR88C681 (% ( (% % + -( ''" ( ( '$ (+ , ( (% & $'$ ( ! '' #+ C2D $ % % C*'3D $" (% (" ' % ( ( %%$ ( C22 2 D ' $ % ( 3$ % % Table 3 Please note that if the Error Mode is "Block" this bit, in the Status Register will remain set, for all subsequent characters, independent of the condition of these received characters, until the "RESET ERROR STATUS" command has been invoked. SRn[3] Transmitter Empty (TXEMT) (% ( (% % %( $ % # (% % + %(%%( + % % ( + '' $ (+ (% '' ( 8 (( %(%%( (% ( (% '$ %( (% $(%$" , (% '' 8 SRn[2] Transmitter Ready (TXRDY) (% (" %" ( $('% 8 (% & $ $& '' '' + , ( (% '$ , (% '' 8" $ (% % '' (% %+$ 5G (% % %( (% ( ((& $ $ (% % %( (% $(%$ '% $$ ( 8 ( %( (% $(%$ ( %($ SRn[1] FIFO Full (FFULL) (% ( (% % '' (% %+$ + 8 $ %+ '%% ( ' +" (" # %(( % ''($ # (% % , $% 8 #+ '' (% (( - ( '% # (% +" 99 ( % , $% 8 SRn[0] Receiver Ready (RXRDY) (% ( ( $('% % '' % '($ $ (% (( - ( # $ & , # (% % '' (% %+$ + 8 $ (% '$ ( , $% % '' ' & %$ ( # Please note that some of the conditions that are flagged by the Status Register can also be programmed to generate an Interrupt Request to the CPU. 8" % ' $(( % +--$ & % -(% ' -$ - # % ' $(( % (%$ 4 N/O ( - 2 N6O ,(& 2 N - (% &$" % (% ' $$ ($ ' '' & ''3( - % -(% SRn[5] Parity Error (% ( (% % CB#8 , #GD C 2 , #GD $% -$ $ (+ '% $( - '' ( $ # % '($ ( ( '' (& #+ 2 $ % % C'D $" (% ( & (% ' + 8 #+ (% ( (% % + -( ''" ( ( '$ (+ '($ (& (% '' ( ! '' #+ C2D $ % % C*'3D $" (% (" ' % ( ( %%$ ( C22 2 D ' $ % ( 3$ % % Table 3 Please note that if the Error Mode is "Block" this bit, in the Status Register will remain set, for all subsequent characters, independent of the condition of these received characters, until the "RESET ERROR STATUS" command has been invoked. SRn[4] Overrun Error #+ %" (% ( ( $('% ''% ( '($ $ %" ( (% % '( + '' # (% + $ '' (% $& ( (( - + & # %(( B (% ''%" '' ( (% ( Please note that unlike the Status Register bits for FE (Framing Error), PE (Parity Error) and RB (Received Break), the OE (Overrun Error) indicator is always flagged on a "Block" Error Mode basis 2 ' $(( (% +--$ '''' %(%" $ & '$ C22 2 D ' $ (% ( 3$ >> XR88C681 H. SPECIAL MODES OF OPERATION H.1 RTS/CTS Handshaking ' -$ % . 8 $%3( -" % % + $ + ' ( $('% (% %'( ( $%'( ' + ( % % % ( ( ( - . 8 $%3( - '(+('&" % ( % 4 '( $ . 8 $%3( %( $ . 8 $%3( H.1.1 Receiver-Controlled RTS/CTS Handshaking # (% $" '( % ((& ('& - %(( - $(' '(+('&" (% $ % '( - %(- (+ (% 8 (% +L $" (% &" & ++'( ( ( - '( 2% Figure 42 % % $(- + ! (%( - ( + '( $ ' +(-( '(( - (' , 5 5 #, %(( - (' * #, 5* 5* * , 99 ,< , 99 5 Figure 42. Block Diagram and Timing Sequence of Two DUARTs Connected in the Receiver-RTS Controlled Configuration >= XR88C681 Figure 42 %% $('%" C'(( ('D $ C %(( - ('D % $('% $ %' '% + ( ( (% ! %+ + $ (% ! (% -( - (- " + ( ( -" +' C'(( - ('D % %( $ C %(( - ('D % '( " (% !" (% %( - + C'(( - ('D $ * + C %(( ('D ! %% ( %%( C'(( - ('D % -$ %' N>O J ''$( - Section G.3" (% %% ( -( - C'(( - ('D + '( $$(( &" C %(( - ('D % -$ %' *N %( + * + C %(( - ('D % -$ $ * ( ' # (% !" C'(( - ('D ' % %(- (% %(- (% +$ $('& ( * ( + %(( - (' #+ 8 + C'(( - ('D (% + % $('$ & 99 ( - -(' C(-D" ( ('& -$ & ( + '( $ +% %E &" * %( + C %(( - ('D ( (% * ( -$ $ ( ($ %( & $ 5 + C'(( - ('D #+ , $% C%D 8 + '(( ('" 8 ( - +" $ 99 ( $(' ( -- +% # (% '%" 99 ( $(' (% ' '$ % ( + , # % % 99 --( - +%" , $ ( (% C -($-D + 99 % # E% , $ %(' (% C# D & C(( -D N>""O J N" " " " " " " O $$%% 2/ (% '( !'% C2 , , 7D $ '%% ,NO -- C(-D $ , ( , -- CD %E &" (% %%$ B( + C'(( - ('D ( %%$ ( + C %(( - ('D (% %%$" % $ $ %(%%( + C %(( - ('D C'(( - ('D (% ($ Figure 42 %% 5 ( '(( - $ + % %%$ 8" ( (% !" (% & '($ '' '%% 8 + C'(( - ('D + 99 ( $(' %% (% %%$ $ + C'(( ('D (% ('& -$ ( '( ' %(- +" %(%%( + * + %(( - (' (%" ' -( " ( (($ Figure 43 % % + $(- (%( - -( '$ %$ ( ( ( - '( $ . 8 $%3( - $ > XR88C681 '(( - (' N>O J %(( - (' *N>O J %% B( ) $$%% 2 (% ( 3% C2 , , *# 7D $ %% , ( " , -(' CD 7 #% 99 %%$T G% (% ('& 7-$ & '( $ '( 7 #% 99 7-$T G% Figure 43. A Flow Diagram Depicting an Algorithm That Could be Used to Apply the Receiver-Controlled RTS/CTS Handshaking Mode H.1.2 Transmitter-Controlled RTS/CTS Handshaking # (% $" %( % ((& - '(( - (' '(+('&" (% $ % %( -& %(- " ( ($ + &( - 8 $ = XR88C681 %(( - (' '(( - (' #, ( , #, ,1 5 5G. ,> 5* , 5G. 5 Figure 44. Block Diagram and Timing Sequence of Two DUARTs Connected in the Transmitter-RTS Controlled Configuration. = XR88C681 Figure 44 %% $('%" $ C %(( - ('D $ " C'(( - ('D (% ! %% ( %%( C %( ('D % -$ %' N6O J " (' %% ( -( - C %(( - ('D + %( (% ! + %%% C %(( - ('D % -$ %' N %( + + C %(( - ('D % -$ $ ( ' # '% + C'(( - ('D" #, ( % -$ - C# , - + D ( E% , +( + # (' ( % (% ( %' (+ #, ( ' - $ #,NO J " , $ C(D N>"" O J N" " " " " " " O $$%% 2/ # (% %" # (' ( $ ( 3 C2 , , *# 7D" $ ( '%% -- ,N1O -(' C(-D $ , ( " ,1" -(' CD (% $" ( " %% ( + C %(( - ('D $ ( %( $ C'(( - ('D ' %( % ($ (% 8 $ + $" ( ( - " ( C %( D + B C %(( - ('D (% --$ C(-D" #, ( (% % --$ C(-D" & - ( C# - + D ( E% , B( #,NO J " (3& # (' ( $ CB(D N>"" O J N" " " " " " " O $$%% / # (% %" # (' ( $ ( 3 C92 , , *# 7D" $ ( '%% -- ,1 C(-D (% $ ( - ( + C %(( - ('D $ ( (( %(%%( + $ + + C %(( - ('D Figure 45 % % (- (' $('% -( '$ %$ ( %( . 8 $%3( - $ Please note that the shaded block pertain to occurrences within the "Receiving Device" B% CB(D '3 ( ( (( C %(( - ('D = XR88C681 2 B( $$%% 2 0 C# , - + D # #, ( '(( - (' P #7, # 22 %(%%( (% ($ 0092 ,1 . ,#7 C9BD B( = $$%% 2 7 #% #, J T G% #% 52 %%$ T G% P (% ('& 7-$ & '( $ '( , --% C8(-D 0092 ,1 . ,#7 C8#08D B( = $$%% #7, # 720 2 %(%%( (% $(%$ 7 G% #% 5G 7-$T 7 Figure 45. A Flow Diagram depicting an Algorithm that could be used to Realize the Transmitter-Controlled RTS/CTS Handshaking Mode H.2 Multi-drop (8051 9 bit) Mode 2' %( ' + ' ' +(-$ ( 3 $ %+ + ($ ('%% ('( % (% %'( ( +(% % ' ' + ( $ +$%" + '( $ '$ + ( - ( ( $ (% $(%'%%$ ( Section H.2.1 =1 H.2.1 Concept of Multi-Drop Mode (% $ (% '( ( %( C7( ( $D + =6 +(& (''% # (% $ + ( C% %( D" ' '$ !( + 6/ % %( (% %%(" % $('$ ( Figure 46 XR88C681 % (' 5 5 5 5 ('% 5 Figure 46. An Illustration Depicting the Concept of Multi-Drop Mode 9* * . = *( ' $$%%. *( Figure 47. Bit Format of Character Data Being Transmitted in the Multi-Drop Mode C% ( D ' ('% C ( %D & %(( - '' &('& & ( C $$%%.D ( +- $$ $ + '' (% &('& %% ( ( (% + ( %($ + & '' &" % % $ ( Figure 47 =< B C% ( D % %( '3 + $ + % %%" ( +(% % $% $$%% & ($ (+(% C- D $$%% & $(++% + $ & ( ( ( (% CD ( $$%% *& $ CD ( *& XR88C681 $$%% *&" " ( % C%D % ' ' !( '($ & % (+ ( ( $(($ % $(' (% ( - $$%%$ '( + $$%%$ % ( $ $ ( + '( + $ &% +% %% $$%%$ ( % ( '(% $(%$" $ ( ' ( (- $ &% +% & ( ( $ -( ! $$%% & (% %($ & C% ('D H.2.2 DUART Multi-Drop Operation -( ' " (( (% -$ ( ( $ & %( - N<41O J C" D # (% $" %($ '' ' %(%% + (" -$ + $ (%" $$%%. . +- (L $ -$ , ( - . J ( $('% '' (% $" ( . J ($ (+(% ( % $$%% Transmitter Operation During Multi-Drop Mode %., ' % % + %($ '' & -( - NO + ' ( $( - $ (% ( 8 ( - NO J CD %% ( . J CD $ %( - NO J CD %% ( . J CD Figure 48 % % '$ + $(- + %(( - ''% $$%% " ( ( ( $ # 3 C22 ,#72D ' $ B( ! ( $ -(% . *( CD B( !!!!!!! -(% . *( CD B( !!!!!!! -(% %( ' (' B( ' 8 %( $$%% ' (' B( ' 8 '% B( '( ('T G% # 3 C22 ,#72D ' $ B( ! ( $ -(% 7 Figure 48. A Flow Diargam Depicting a Procedure That Can Be Used to Transmit Characters in the Multi-Drop Mode =6 XR88C681 Receiver Operation During Multi-Drop Mode B ' % -$ ( ( $" $ '( % $(%$ &(' ' +(-( " '( ( $ '' ( 8 $ % 5G ( $(' $. ( (+ . ( (% CD $$%% +- 8" '' ( $(%'$$ (+ (% . ( (% CD +- +" ( % % 5G ( $('" , %$ $ '($ '' $ $( (+ $$%% ( % % '% + , #+ $$%%% $ '" ( $('( - ( (% - " , %$ '(" ( ( + %%E '3% + $ ' '( % $ '( ( ( '%%$ % ( 7 ( '($ ''% ''%%( , & $( 8 % + . +- ( (% ( N6O" % -(% ( & %$ ( $(' C,(& 2D +" ( ' M '( ( '( ' ''" , %$ ' ( ( N6O ( $ (+& ( (% CD ''% ' C- , D $'% $$%% ''" N6O JCD" ( %$ ' (% $$%% ( (% #+ $$%%% $ '" (% , (% ( $$ '(( + ! '3 + $" $ %$ $(% '( Figure 49 % % + $(- $('( - ' $$ '$ + $( - '($ ''% ( ( ( $ '( (% (%$ (% $$ ( ( $ N<41O J N" O % 7& '($ $$%% ' , $$%% T 7 M' ' '( ( % (%$ G% 2 '( B( ! ( $ -(% 7 8% 5G # $(' %%$ T G% $ ( $$%% ' + 8 $ ( ' + 8 '3 N6O 7 #% 7 ' ' N6O J T G% Figure 49. A Flow Diagram Depicting a Procedure That Can Be Used to Receive Characters in the Multi-Drop Mode. =/ XR88C681 H.3 Standby Mode & '$ ( % $& $ ' % (% ( (% E($ %" ( ( C #;2 ,2 #7D $ C2 7*G 2D ' $ (%%$ ( ' $ -(% $(%% ''3% $(' !' + '&% %'(" (' %(- (+(' & $'% ( - ' # (% $ & + '( % (' ( ''& $( ( " (( - $ C2 #;2 2D ' $ " % ( 3$ ( $ -(%" %% $(' ( (( 6* % %( - %(% $ '(% $ (( - ( # # %3 -(% + -( - ( $& $ (% ' $$ & %(% ( % + ( - - $ '( %$ -$ + C2 #;2 2D ' $ %( ' -(% ' % - $ ( % $( - % $& $ '( ( ' % %$ ( $ % I. COMMENTS ABOUT THE XR88C681 IN 28 PIN DIP PACKAGE ' + (% $ % $(%'%%$ +% (' ( % (' '3-$ ( < ( #, << ( ,9 8" '% + $'$ + ( % % ( = ( '3- $ +( - +% REGISTER SUMMARY Bit 7 Rx RTS Control J 7 J G% Bit 6 Rx Int Select J5G J 99 Bit 5 Error Mode J J *'3 Bit 4 Parity Mode Bit 3 Select Bit 2 Parity Select J 2 J $$ Bit 1 Bit 0 ( ?$ (% (% $ '3 + # :" #2#" $ #2 ( % + $ %3( - + '( % (% (% $ '3 + & ( % J. PROGRAMMING ( + (% -$ & (( - ' $% ( ( -(%%" ( ( +$'3 (% ($$ & %% -(%% (' ' $ & , -(% $$%%( - (% % ( $ % '% ' % + " #" #" ," $ , -(%% $ ( (((I% #; / ( - ( " ' %$ !'(%$ (+ ' % + ' -(%% ' -$" %( ' '( ' -% & % ( ( ( 2!4 -( - + (% '' ( $ (% ( - '($ & % ( '( + % '' # - " ' -% -(%% (' ' '( %( ( %$ $ & ( %( '( $(%$" $ '( ' -% %$ $ & . (% %$ $" ' $" ''3 %'" $ %% -(%% $('$ + ' ' ($ ( $ $ ( Table 29 - Table 41 %(I% ( %%(- % + ' -(% Number of Bits/Char. J 6 J / J > J = J B( ,(& J ' ,(& J 7 ,(& J ( $ Table 29. Mode Registers 1: MR1A, MR1B => XR88C681 Bit 7 Bit 6 Bit 5 Tx RTS Control J 7 J G% Bit 4 CTS Enable Tx J 7 J G% J 6/1 J /6 J /== 1 J >6 < J =1 6 J =>6 / J 1= > J Bit 3 Bit 2 Bit 1 Bit 0 Channel Mode J 7 J 2' J 9' 9 J 9 Stop Bit Length = J 6/1 J /6 J /== * J >6 J =1 J =>6 2 J 1= J Table 30. Mode Register 2: MR2A, MR2B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Receiver Clock Select Table 9 Transmitter Clock Select Table 9 Table 31. Clock Select Registers: CSRA, CSRB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Miscellaneous Commands ! ( Section B.2 Enable/Disable Tx J 7 - J 2 ! J (% ! J 7 $ 7 % Enable/Disable Rx J 7 - J 2 ! J (% ! J 7 $ 7 % Table 32. Command Registers: CRA, CRB Bit 7 Received Break J 7 J G% Bit 6 Framing Error J 7 J G% Bit 5 Parity Error J 7 J G% Bit 4 Overrun Error J 7 J G% Bit 3 TXEMT J 7 J G% Bit 2 TXRDY J 7 J G% Bit 1 FFULL J 7 J G% Bit 0 RXRDY J 7 J G% Table 33. Status Registers: SRA, SRB Bit 7 OP7 J,N>O J5G* Bit 6 OP6 J,N/O J5G Bit 5 OP5 J,N6O J5G. 99* Bit 4 OP4 J,N == XR88C681 Bit 7 BRG Set Select J J Bit 6 Bit 5 Bit 4 Bit 3 Delta IP3 Interrupt J J 7 Bit 2 Delta IP2 Interrupt J J 7 Bit 1 Delta IP1 Interrupt J J 7 Bit 0 Delta IP0 Interrupt J J 7 Counter/Timer #1 Mode and Source Table 7 Table 35. Auxiliary Control Register: ACR Bit 7 Delta IP3 J 7 J G% Bit 6 Delta IP2 J 7 J G% Bit 5 Delta IP1 J 7 J G% Bit 4 Delta IP0 J 7 J G% Bit 3 IP3 J 9 J 8(- Bit 2 IP2 J 9 J 8(- Bit 1 IP1 J 9 J 8(- Bit 0 IP0 J 9 J 8(- Table 36. Input Port Configuration Register , IPCR Bit 7 Input Port Change J 7 J G% Bit 6 Delta Break B J 7 J G% Bit 5 RXRDY/ FFULLB J 7 J G% Bit 4 TXRDYB J 7 J G% Bit 3 Counter #1 Ready J 7 J G% Bit 2 Delta Break A J 7 J G% Bit 1 RXRDY/ FFULLA J 7 J G% Bit 0 TXRDYA J 7 J G% Table 37. Interrupt Status Register, ISR Bit 7 Input Port Change Bit 6 Delta Break B Bit 5 RXRDY/ FFULLB Bit 4 TXRDYB J ++ Bit 3 Counter #1 Ready Bit 2 Delta Break A Bit 1 RXRDY/ FFULLA Bit 0 TXRDYA J ++ J J ++ J J ++ J J ++ J J J ++ J J ++ J J ++ J Table 38. Interrupt Mask Register, IMR Bit 7 .6 Bit 6 .< Bit 5 .1 Bit 4 . Bit 3 . Bit 2 . Bit 1 . Bit 0 .= Table 39. Counter/Timer Upper Byte Register, CTUR Bit 7 .> Bit 6 ./ Bit 5 .6 Bit 4 .< Bit 3 .1 Bit 2 . Bit 1 . Bit 0 . Table 40. Counter/Timer Lower Byte Register, CTLR Bit 7 #;> Bit 6 #;/ Bit 5 #;6 Bit 4 #;< Bit 3 #;1 Bit 2 #; Bit 1 #; Bit 0 #; Table 41. Interrupt Vector Register: IVR = XR88C681 K. TIMING DIAGRAMS ; <; =; % 9% ; =; Figure 50. Input and Output Levels for Timing Measurements Note: AC testing inputs are driven at 0.4V for a logic "0" and 2.4V for a logic "1" except for -40 to 85(C and -55 to 125(C, logic "1" shall be 2.6V. Timing measurements are made at 0.8V for a logic "0" and 2.0V for a logic "1". 22 2 Figure 51. Reset Timing XR88C681 1 8 B > $ 9 7 ; 9# ; 9# 9 8 B B B > B( 8 ; 9# Figure 52. XR88C681 Read and Write Cycle Timing XR88C681 #7 # : # 8 # B 2# > 9 #2# # 2 7 ; 9# ;2 9 #2 # 22 # 7 Figure 53. XR88C681 Z Mode Interrupt Cycle Timing XR88C681 , #, #,/ ,8 B , ,> 9 , 72B Figure 54. Port Timing B # # Figure 55. Interrupt Timing 1 XR88C681 4 4 4 4 A & Q 6 A & Q 6 4 6 A & Q 6 4 6 A & Q 6 5 XR88C681 1/=/<8I , % &% 5 1/=/<8I 5 XR88C681 5 , % &% 9: 5.9: . 9: 5 5 9: 5 5 Figure 56. Clock Timing < XR88C681 5 # 5 5 *( ( / '3% 5 5 Figure 57. Transmitter Timing 5 5 # 5 5 58 Figure 58. Receiver Timing 6 XR88C681 44 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) Rev. 1.00 D D << 45 x H2 45 x H1 C ( - , A2 B1 D D1 D3 BD 2 e R D3 A1 A INCHES SYMBOL * * 1 8 8 MIN /6 1 / = /=6 /6 6 MAX = UUU 1 1 /6 /6/ /1 MILLIMETERS MIN < 6 11 // >< /6 < MAX <6> 16 UUU 61 = 1 >/6 /// / 6 & 6 * < < 6 6/ <= <6 > & > * > > /< < < Note: The control dimension is the inch column / XR88C681 40 LEAD CERAMIC DUAL-IN-LINE (600 MIL CDIP) Rev. 1.00 < E D Base Plane Seating Plane L e B B1 c A1 A E1 INCHES SYMBOL * * ' 2 2 9 MIN 6 < <6 = 66 MAX 6 >6 / /6 = / MILLIMETERS MIN 6< 1= 1/ < 666 1> MAX 6> // /6 / * * 6 6 6< * 6< * 1= 6= 6 Note: The control dimension is the inch column > XR88C681 40 LEAD PLASTIC DUAL-IN-LINE (600 MIL PDIP) Rev. 1.00 < E1 D E A2 Seating Plane A L B e B1 A1 eA eB C INCHES SYMBOL * * 2 2 * 9 MIN / 6 6 < 1 = = / <=6 MAX 6 > 6 < > < 6 /6 6= MILLIMETERS MIN / 6 6< 1 MAX /16 >= <6 6/ >= 1= 61 6== <>1 * / * / 6 > 6 6< * 6< * 6< >>= 6= 6 Note: The control dimension is the inch column = XR88C681 7#2 25 ( %% (- 3 ' -% $'% ' ( $ ( (% ('( ( $ ( $%(- " + ' (((& 25 ( %%% % %(((& + % + & '('(% $ %'($ ( " ' &% (' % $ & (-" $ 3% % ( '('(% + + ( +( - % $ %'$% ' ( $ ( & + (%( %% $ & & $ $( - %H% %'(+(' ('( B( ( +( ( (% ('( % '+& ''3$L % %(((&" " (% %%$ + ( '''(% 25 ( $% ' $ % + & + (% $'% ( (+ % ('( % +( + '( + $' ' % & !'$ '% +( + (+ % %&% %(- (+(' & ++' (% %+& ++'( %% ,$'% (I$ + % ( %' ('( % %% 25 ( '(%" ( (( -" %% '% (% %(%+'( 4 (%3 + ( M& $- % ( ((I$L % %%% %' (%3%L ' ( (((& + 25 ( (% $E& '$ $ '(' % '% &(- 25 ( % $'( " ( " ( ( ( ' % + 25 ( (% (($ |
Price & Availability of XR88C681CN40
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |